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forked from tanchou/Verilog

Refactor UART testbench for ultrasonic commands: improve readability and organization of code structure

This commit is contained in:
Gamenight77
2025-05-12 13:24:58 +02:00
parent 30bbe27510
commit 790b85841b

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@@ -3,69 +3,89 @@
module tb_ultrason_commands; module tb_ultrason_commands;
reg clk = 0; reg clk = 0;
always #18.5 clk = ~clk; // ~27 MHz
wire tx, rx;
wire [5:0] leds;
wire ultrason_sig;
reg tx_enable = 0; reg tx_enable = 0;
reg tx_ready; wire tx_ready;
reg [7:0] data_in = 8'h00; reg [7:0] data_in = 8'h00;
reg [7:0] data_out; wire [7:0] data_out;
wire rx_received;
reg rx_received;
wire rx_enable = 1'b1;
wire rx,tx;
always #18.5 clk = ~clk;
// === PARAMÈTRES ===
localparam CLK_FREQ = 27_000_000; localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200; localparam BAUD_RATE = 115_200;
ultrasonic_sensor ultrasonic_sensor_instance ( // === MODULE TESTÉ ===
.clk(clk), top_uart_ultrason_command dut (
.signal(ultrason_sig)
);
top_uart_ultrason_command top_uart_ultrason_command_instance (
.clk(clk), .clk(clk),
.rx(rx), .rx(rx),
.tx(tx), .tx(tx),
.ultrason_sig(ultrason_sig), .ultrason_sig(ultrason_sig),
.leds() .leds(leds)
); );
// === SIMULATION CAPTEUR ULTRASON ===
ultrasonic_sensor fake_sensor (
.clk(clk),
.signal(ultrason_sig)
);
// === RX : observe ce que le FPGA envoie ===
uart_rx #( uart_rx #(
.CLK_FREQ(CLK_FREQ), .CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE) .BAUD_RATE(BAUD_RATE)
) rx_instance ( ) uart_rx_inst (
.clk(clk), .clk(clk),
.rx_pin(tx), .rx_pin(tx), // observe ce que le FPGA envoie
.rx_data(data_out), .rx_data(data_out),
.rx_received(rx_received), .rx_received(rx_received),
.rx_enable(rx_enable) .rx_enable(1'b1)
); );
// === TX : envoie une commande au FPGA ===
uart_tx #( uart_tx #(
.CLK_FREQ(CLK_FREQ), .CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE) .BAUD_RATE(BAUD_RATE)
)tx_instance ( ) uart_tx_inst (
.clk(clk), .clk(clk),
.tx_enable(tx_enable), .tx_enable(tx_enable),
.tx_ready(tx_ready), .tx_ready(tx_ready),
.data(data_in), .data(data_in),
.tx(rx), .tx(rx), // vers le FPGA
.rst_p(1'b0) .rst_p(1'b0)
); );
// === TEST SEQUENCE ===
initial begin initial begin
$dumpfile("runs/uart.vcd"); $dumpfile("runs/ultrason_commands.vcd");
$dumpvars(0, tb_uart); $dumpvars(0, tb_ultrason_commands);
$display("======== Start UART ULTRASONIC COMMANDS ========="); $display("==== Start UART Ultrasonic Test ====");
// Attendre que le tx soit prêt
wait(tx_ready);
#100;
$display("======== END UART ULTRASONIC COMMANDS ========="); // Envoyer la commande "ONE" (1)
data_in <= 8'd1; // ONE
tx_enable <= 1;
#20;
tx_enable <= 0;
// Attendre la réponse
wait(rx_received);
$display(">> Distance LSB: %d", data_out);
wait(rx_received);
$display(">> Distance MSB: %d", data_out);
$display("==== End UART Ultrasonic Test ====");
#1000; #1000;
$stop; $stop;
end end
endmodule endmodule