Training exercise

Introduction/bidouille/7458.v

@@ -0,0 +1,28 @@
+module top_module ( 
+    input p1a, p1b, p1c, p1d, p1e, p1f,
+    output p1y,
+    input p2a, p2b, p2c, p2d,
+    output p2y );
+	
+    wire tand1;
+    wire tand2;
+
+    wire and1;
+    wire and2;
+
+    wire or1;
+    wire or2;
+
+    assign tand1 = p1a & p1b & p1c;
+    assign tand2 = p1d & p1e & p1f;
+
+    assign and1 = p2a & p2b;
+    assign and2 = p2c & p2d;
+
+    assign or1 = tand1 | tand2;
+    assign or2 = and1 | and2;
+
+    assign p1y = or1;
+    assign p2y = or2;
+
+endmodule

Introduction/bidouille/Bitwise_Logical.v

@@ -0,0 +1,14 @@
+module top_module( 
+    input [2:0] a,
+    input [2:0] b,
+    output [2:0] out_or_bitwise,
+    output out_or_logical,
+    output [5:0] out_not
+);
+
+    assign out_or_bitwise = a | b;
+    assign out_or_logical = a || b;
+    assign out_not[2:0] = ~a;
+    assign out_not[5:3] = ~b;
+
+endmodule

Introduction/bidouille/Gates4.v

@@ -0,0 +1,12 @@
+module top_module( 
+    input [3:0] in,
+    output out_and,
+    output out_or,
+    output out_xor
+);
+
+    assign out_and  = in[0] & in[1] & in[2] & in[3];
+    assign out_or   = in[0] | in[1] | in[2] | in[3];
+    assign out_xor  = in[0] ^ in[1] ^ in[2] ^ in[3];
+
+endmodule

Introduction/bidouille/Vector3_concat.v

@@ -0,0 +1,7 @@
+module top_module (
+    input [4:0] a, b, c, d, e, f,
+    output [7:0] w, x, y, z );//
+
+    assign { w, x, y, z } = { a, b, c, d, e, f, 2'b11};
+
+endmodule

Introduction/bidouille/vector.v

@@ -0,0 +1,14 @@
+module top_module ( 
+    input wire [2:0] vec,
+    output wire [2:0] outv,
+    output wire o2,
+    output wire o1,
+    output wire o0  ); 
+
+    assign outv = vec;
+
+    assign o0 = vec[0];
+    assign o1 = vec[1];
+    assign o2 = vec[2];
+
+endmodule