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Fix build script and update state machine in UART loopback module

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Gamenight77
2025-05-07 10:39:52 +02:00
parent ec1c69cf8f
commit 83c40bee28
4 changed files with 181 additions and 2 deletions
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1
Semaine_4/UART_ULTRASON/IP/verilog/ultrasonic_fpga.v
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@@ -53,6 +53,7 @@ module ultrasonic_fpga #(
case (state)
IDLE: begin
done <= 1;
sig_out <= 0;
sig_dir <= 0;
distance <= 0;

2
Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v
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@@ -56,7 +56,7 @@ module top_uart_ultrason (
SEND_LOW: begin
wr_en <= 1;
wr_data <= distance[7:0]; // Octet LSB
state <= IDLE;
state <= SEND_HIGH;
end
SEND_HIGH: begin