Fix build script and update state machine in UART loopback module

2025-05-07 10:39:52 +02:00
parent ec1c69cf8f
commit 83c40bee28
4 changed files with 181 additions and 2 deletions
--- a/Semaine_4/UART_ULTRASON/IP/verilog/ultrasonic_fpga.v
+++ b/Semaine_4/UART_ULTRASON/IP/verilog/ultrasonic_fpga.v
@@ -53,6 +53,7 @@ module ultrasonic_fpga #(
        
        case (state)
            IDLE: begin
+                done <= 1;
                sig_out <= 0;
                sig_dir <= 0;
                distance <= 0;