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Add DHT11 interface and UART integration for ultrasonic sensor project

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- Created DHT11 interface in Verilog to handle communication with DHT11 sensor.
- Implemented LED control logic to indicate sensor status and data readiness.
- Added project scripts for building, cleaning, and simulating the design.
- Established constraints for FPGA pin assignments.
- Developed testbench for DHT11 UART communication.
- Updated README files to reflect project functionality and commands.
This commit is contained in:
Gamenight77
2025-05-14 14:40:16 +02:00
parent 6a5b90c8d1
commit 861c9869f5
26 changed files with 1149 additions and 21 deletions
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2
Semaine_5/DHT11/scripts/simulate.bat
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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=dht11_interface
set TOP=tb_dht11
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog

35
Semaine_5/DHT11/src/verilog/dht11_interface.v
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@@ -1,18 +1,19 @@
module dht11_interface (
input wire i_clk, // 27 MHz
module dht11_interface #(
parameter CLK_FREQ = 27_000_000
)(
input wire i_clk,
inout wire io_dht11_sig,
input wire i_start,
output reg o_dht11_data_ready,
output reg o_busy,
output wire [7:0] o_temp_data,
output wire [7:0] o_hum_data,
output reg [7:0] o_temp_data,
output reg [7:0] o_hum_data,
output reg o_dht11_error
);
// === DHT11 INTERFACE ===
// === PARAMÈTRES ===
parameter CLK_FREQ = 27_000_000;
localparam T_18MS = CLK_FREQ * 18 / 1000; // cycles pour 18ms
localparam T_80US = CLK_FREQ * 81 / 1_000_000;
localparam T_79US = CLK_FREQ * 79 / 1_000_000;
@@ -22,6 +23,7 @@ module dht11_interface (
localparam T_49US = CLK_FREQ * 49 / 1_000_000;
localparam T_40US = CLK_FREQ * 40 / 1_000_000;
localparam T_28US = CLK_FREQ * 28 / 1_000_000;
localparam T_26US = CLK_FREQ * 26 / 1_000_000;
localparam T_20US = CLK_FREQ * 20 / 1_000_000;
@@ -43,6 +45,17 @@ module dht11_interface (
reg [5:0] bit_index;
reg [39:0] raw_data;
// === FSM ===
localparam IDLE = 4'd0, // Pull up la ligne
START = 4'd1, // Pull low 18ms
WAIT_RESPONSE = 4'd2, // Release la ligne (entre 20 et 40us)
RESPONSE_LOW = 4'd3, // DHT11 pull low 80us
RESPONSE_HIGH = 4'd4, // DHT11 pull high 80us
READ_BITS_LOW = 4'd5,
READ_BITS_HIGH = 4'd6,
DONE = 4'd7,
ERROR = 4'd8;
// === INITIALISATION ===
initial begin
sig_dir = 0;
@@ -54,18 +67,6 @@ module dht11_interface (
o_dht11_data_ready = 0;
o_dht11_error = 0;
end
// === FSM ===
localparam IDLE = 4'd0, // Pull up la ligne
START = 4'd1, // Pull low 18ms
WAIT_RESPONSE = 4'd2, // Release la ligne (entre 20 et 40us)
RESPONSE_LOW = 4'd3, // DHT11 pull low 80us
RESPONSE_HIGH = 4'd4, // DHT11 pull high 80us
READ_READ_BITS_LOW = 4'd5,
READ_READ_BITS_HIGH = 4'd6,
DONE = 4'd7,
ERROR = 4'd8;
// === FSM principale ===
always @(posedge i_clk) begin

110
Semaine_5/DHT11/src/verilog/dht_sensor_sim.v Normal file
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@@ -0,0 +1,110 @@
module dht11_sensor_sim(
inout wire sig,
input wire clk
);
reg sig_out = 1;
reg sig_dir = 0; // 0 = haute impédance (entrée), 1 = output (écriture)
assign sig = sig_dir ? sig_out : 1'bz;
// Clk counter pour timings
reg [31:0] clk_counter = 0;
// FSM
reg [3:0] state = 0;
// Constantes de timing (à 27 MHz)
localparam T_80US = 2160; // 27MHz * 80us
localparam T_50US = 1350;
localparam T_70US = 1890;
localparam T_28US = 756;
// Données à envoyer (40 bits : Humidité, Humidité décimale, Température, Température décimale, checksum)
reg [39:0] data_to_send = {8'd55, 8'd0, 8'd23, 8'd0, 8'd78}; // 55 + 0 + 23 + 0 = 78
reg [5:0] bit_index = 0;
always @(posedge clk) begin
clk_counter <= clk_counter + 1;
case (state)
0: begin // Attente du signal LOW pendant ~18ms
if (sig === 1'b0) begin
clk_counter <= 0;
state <= 1;
end
end
1: begin // Confirmer que LOW dure assez longtemps
if (sig === 1'b1) begin
if (clk_counter >= 480_000) begin // ~18ms @27MHz
clk_counter <= 0;
state <= 2;
end else begin
state <= 0; // reset si trop court
end
end
end
2: begin // Capteur tire LOW pendant 80µs
sig_dir <= 1;
sig_out <= 0;
if (clk_counter >= T_80US) begin
clk_counter <= 0;
state <= 3;
sig_out <= 1; // ensuite tire HIGH
end
end
3: begin // Capteur tire HIGH pendant 80µs
if (clk_counter >= T_80US) begin
clk_counter <= 0;
bit_index <= 0;
state <= 4;
sig_dir <= 0; // libère la ligne pour début d'envoi
end
end
4: begin // Attente que host tire la ligne LOW (début bit start)
if (sig === 1'b0) begin
clk_counter <= 0;
state <= 5;
end
end
5: begin // Attente du front montant (bit start terminé)
if (sig === 1'b1) begin
clk_counter <= 0;
sig_dir <= 1;
sig_out <= 1; // commence bit
state <= 6;
end
end
6: begin // Envoi du bit en fonction de la valeur
if (clk_counter == T_50US) begin
sig_out <= 0; // fin du bit
clk_counter <= 0;
state <= 7;
end
end
7: begin // Repos entre les bits
if (clk_counter == (data_to_send[39 - bit_index] ? T_70US : T_28US)) begin
clk_counter <= 0;
sig_dir <= 0; // libère la ligne
bit_index <= bit_index + 1;
if (bit_index == 39)
state <= 8; // Terminé
else
state <= 4;
end
end
8: begin
// Tout est terminé. On reste ici.
end
endcase
end
endmodule

38
Semaine_5/DHT11/tests/verilog/tb_dht11.v
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@@ -5,11 +5,32 @@ module tb_dht11;
reg clk = 0;
always #18.5 clk = ~clk; // Génère une clock 27 MHz
// === Simulation du module DHT11 ===
// === Registres ===
wire io_dht11_sig;
reg dht11_start;
wire dht11_data_ready;
wire dht11_busy;
wire [7:0] dht11_temp_data;
wire [7:0] dht11_hum_data;
wire dht11_error;
// === Simulation du module DHT11 ===
dht11_sensor_sim dht11_sim (
.sig(io_dht11_sig),
.clk(clk)
);
// === Module DHT11 INTERFACE ===
dht11_interface dht11_interface (
.i_clk(clk),
.io_dht11_sig(io_dht11_sig),
.i_start(dht11_start),
.o_dht11_data_ready(dht11_data_ready),
.o_busy(dht11_busy),
.o_temp_data(dht11_temp_data),
.o_hum_data(dht11_hum_data),
.o_dht11_error(dht11_error)
);
// === TEST SEQUENCE ===
initial begin
@@ -18,7 +39,18 @@ module tb_dht11;
$display("==== Start DHT11 Test ====");
#100;
dht11_start = 1; // Démarre la lecture des données
$display("DHT11 start...");
wait(dht11_busy); // Attend que le module soit occupé
$display("DHT11 busy...");
wait(dht11_data_ready); // Attend que les données soient prêtes
$display("DHT11 data ready...");
$display("Température : %d.%d °C", dht11_temp_data);
$display("Humidité : %d.%d %%", dht11_hum_data);
$display("==== End DHT11 Test ====");
$finish;