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Add DHT11 interface and UART integration for ultrasonic sensor project

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- Created DHT11 interface in Verilog to handle communication with DHT11 sensor.
- Implemented LED control logic to indicate sensor status and data readiness.
- Added project scripts for building, cleaning, and simulating the design.
- Established constraints for FPGA pin assignments.
- Developed testbench for DHT11 UART communication.
- Updated README files to reflect project functionality and commands.
This commit is contained in:
Gamenight77
2025-05-14 14:40:16 +02:00
parent 6a5b90c8d1
commit 861c9869f5
26 changed files with 1149 additions and 21 deletions
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35
Semaine_5/DHT11/src/verilog/dht11_interface.v
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@@ -1,18 +1,19 @@
module dht11_interface (
input wire i_clk, // 27 MHz
module dht11_interface #(
parameter CLK_FREQ = 27_000_000
)(
input wire i_clk,
inout wire io_dht11_sig,
input wire i_start,
output reg o_dht11_data_ready,
output reg o_busy,
output wire [7:0] o_temp_data,
output wire [7:0] o_hum_data,
output reg [7:0] o_temp_data,
output reg [7:0] o_hum_data,
output reg o_dht11_error
);
// === DHT11 INTERFACE ===
// === PARAMÈTRES ===
parameter CLK_FREQ = 27_000_000;
localparam T_18MS = CLK_FREQ * 18 / 1000; // cycles pour 18ms
localparam T_80US = CLK_FREQ * 81 / 1_000_000;
localparam T_79US = CLK_FREQ * 79 / 1_000_000;
@@ -22,6 +23,7 @@ module dht11_interface (
localparam T_49US = CLK_FREQ * 49 / 1_000_000;
localparam T_40US = CLK_FREQ * 40 / 1_000_000;
localparam T_28US = CLK_FREQ * 28 / 1_000_000;
localparam T_26US = CLK_FREQ * 26 / 1_000_000;
localparam T_20US = CLK_FREQ * 20 / 1_000_000;
@@ -43,6 +45,17 @@ module dht11_interface (
reg [5:0] bit_index;
reg [39:0] raw_data;
// === FSM ===
localparam IDLE = 4'd0, // Pull up la ligne
START = 4'd1, // Pull low 18ms
WAIT_RESPONSE = 4'd2, // Release la ligne (entre 20 et 40us)
RESPONSE_LOW = 4'd3, // DHT11 pull low 80us
RESPONSE_HIGH = 4'd4, // DHT11 pull high 80us
READ_BITS_LOW = 4'd5,
READ_BITS_HIGH = 4'd6,
DONE = 4'd7,
ERROR = 4'd8;
// === INITIALISATION ===
initial begin
sig_dir = 0;
@@ -54,18 +67,6 @@ module dht11_interface (
o_dht11_data_ready = 0;
o_dht11_error = 0;
end
// === FSM ===
localparam IDLE = 4'd0, // Pull up la ligne
START = 4'd1, // Pull low 18ms
WAIT_RESPONSE = 4'd2, // Release la ligne (entre 20 et 40us)
RESPONSE_LOW = 4'd3, // DHT11 pull low 80us
RESPONSE_HIGH = 4'd4, // DHT11 pull high 80us
READ_READ_BITS_LOW = 4'd5,
READ_READ_BITS_HIGH = 4'd6,
DONE = 4'd7,
ERROR = 4'd8;
// === FSM principale ===
always @(posedge i_clk) begin