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forked from tanchou/Verilog

Add DHT11 interface and UART integration for ultrasonic sensor project

- Created DHT11 interface in Verilog to handle communication with DHT11 sensor.
- Implemented LED control logic to indicate sensor status and data readiness.
- Added project scripts for building, cleaning, and simulating the design.
- Established constraints for FPGA pin assignments.
- Developed testbench for DHT11 UART communication.
- Updated README files to reflect project functionality and commands.
This commit is contained in:
Gamenight77
2025-05-14 14:40:16 +02:00
parent 6a5b90c8d1
commit 861c9869f5
26 changed files with 1149 additions and 21 deletions

View File

@@ -5,11 +5,32 @@ module tb_dht11;
reg clk = 0;
always #18.5 clk = ~clk; // Génère une clock 27 MHz
// === Simulation du module DHT11 ===
// === Registres ===
wire io_dht11_sig;
reg dht11_start;
wire dht11_data_ready;
wire dht11_busy;
wire [7:0] dht11_temp_data;
wire [7:0] dht11_hum_data;
wire dht11_error;
// === Simulation du module DHT11 ===
dht11_sensor_sim dht11_sim (
.sig(io_dht11_sig),
.clk(clk)
);
// === Module DHT11 INTERFACE ===
dht11_interface dht11_interface (
.i_clk(clk),
.io_dht11_sig(io_dht11_sig),
.i_start(dht11_start),
.o_dht11_data_ready(dht11_data_ready),
.o_busy(dht11_busy),
.o_temp_data(dht11_temp_data),
.o_hum_data(dht11_hum_data),
.o_dht11_error(dht11_error)
);
// === TEST SEQUENCE ===
initial begin
@@ -18,7 +39,18 @@ module tb_dht11;
$display("==== Start DHT11 Test ====");
#100;
dht11_start = 1; // Démarre la lecture des données
$display("DHT11 start...");
wait(dht11_busy); // Attend que le module soit occupé
$display("DHT11 busy...");
wait(dht11_data_ready); // Attend que les données soient prêtes
$display("DHT11 data ready...");
$display("Température : %d.%d °C", dht11_temp_data);
$display("Humidité : %d.%d %%", dht11_hum_data);
$display("==== End DHT11 Test ====");
$finish;