Add DHT11 interface and UART integration for ultrasonic sensor project

- Created DHT11 interface in Verilog to handle communication with DHT11 sensor.
- Implemented LED control logic to indicate sensor status and data readiness.
- Added project scripts for building, cleaning, and simulating the design.
- Established constraints for FPGA pin assignments.
- Developed testbench for DHT11 UART communication.
- Updated README files to reflect project functionality and commands.

Semaine_5/DHT11_LEDS/scripts/build.bat

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+@echo off
+setlocal
+
+rem === Aller à la racine du projet ===
+cd /d %~dp0\..
+
+rem === Config de base ===
+set DEVICE=GW2AR-LV18QN88C8/I7
+set BOARD=tangnano20k
+set TOP=dht11_leds
+set CST_FILE=%TOP%.cst
+set JSON_FILE=runs/%TOP%.json
+set PNR_JSON=runs/pnr_%TOP%.json
+set BITSTREAM=runs/%TOP%.fs
+
+rem === Créer le dossier runs si nécessaire ===
+if not exist runs (
+    mkdir runs
+)
+
+echo === Étape 1 : Synthèse avec Yosys ===
+yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/dht11_interface.v; synth_gowin -top %TOP% -json %JSON_FILE%"
+if errorlevel 1 goto error
+
+echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===
+nextpnr-himbaechel --json %JSON_FILE% --write %PNR_JSON% --device %DEVICE% --vopt cst=constraints/%CST_FILE% --vopt family=GW2A-18C
+if errorlevel 1 goto error
+
+echo === Étape 3 : Packing avec gowin_pack ===
+gowin_pack -d %DEVICE% -o %BITSTREAM% %PNR_JSON%
+if errorlevel 1 goto error
+
+echo === Étape 4 : Flash avec openFPGALoader ===
+openFPGALoader -b %BOARD% %BITSTREAM%
+if errorlevel 1 goto error
+
+echo === Compilation et flash réussis ===
+goto end
+
+:error
+echo === Une erreur est survenue ===
+
+:end
+endlocal
+pause