forked from tanchou/Verilog
Add DHT11 interface and UART integration for ultrasonic sensor project
- Created DHT11 interface in Verilog to handle communication with DHT11 sensor. - Implemented LED control logic to indicate sensor status and data readiness. - Added project scripts for building, cleaning, and simulating the design. - Established constraints for FPGA pin assignments. - Developed testbench for DHT11 UART communication. - Updated README files to reflect project functionality and commands.
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58
Semaine_5/DHT11_LEDS/src/verilog/dht11_leds.v
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58
Semaine_5/DHT11_LEDS/src/verilog/dht11_leds.v
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module dht11_leds (
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input wire clk, // 27 MHz
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inout wire dht11_sig,
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input wire start,
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output reg [5:0] leds
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);
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// === Registres ===
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wire io_dht11_sig;
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reg dht11_start;
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wire dht11_data_ready;
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wire dht11_busy;
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wire [7:0] dht11_temp_data;
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wire [7:0] dht11_hum_data;
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wire dht11_error;
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dht11_interface dht11_interface (
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.i_clk(clk),
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.io_dht11_sig(io_dht11_sig),
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.i_start(dht11_start),
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.o_dht11_data_ready(dht11_data_ready),
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.o_busy(dht11_busy),
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.o_temp_data(dht11_temp_data),
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.o_hum_data(dht11_hum_data),
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.o_dht11_error(dht11_error)
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);
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initial begin
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dht11_start = 0;
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leds = 6'b000000;
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end
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always @(posedge clk) begin
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if (start) begin
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dht11_start = 1; // Démarre la lecture des données
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leds[0] = 1; // LED verte allumée
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end else begin
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dht11_start = 0; // Arrête la lecture des données
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leds[0] = 0; // LED verte éteinte
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end
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if (dht11_busy) begin
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leds[1] = 1; // LED jaune allumée
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end else begin
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leds[1] = 0; // LED jaune éteinte
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end
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if (dht11_data_ready) begin
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leds = {dht11_temp_data[7:4], dht11_hum_data[7:4]}; // Affiche les données sur les LEDs
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end
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if (dht11_error) begin
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leds[5:3] = 3'b111; // Toutes les LEDs allumées en cas d'erreur
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end else begin
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leds[5:3] = 3'b000; // Éteint les LEDs si pas d'erreur
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end
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end
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endmodule
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