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Add DHT11 interface and UART integration for ultrasonic sensor project

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- Created DHT11 interface in Verilog to handle communication with DHT11 sensor.
- Implemented LED control logic to indicate sensor status and data readiness.
- Added project scripts for building, cleaning, and simulating the design.
- Established constraints for FPGA pin assignments.
- Developed testbench for DHT11 UART communication.
- Updated README files to reflect project functionality and commands.
This commit is contained in:
Gamenight77
2025-05-14 14:40:16 +02:00
parent 6a5b90c8d1
commit 861c9869f5
26 changed files with 1149 additions and 21 deletions
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5
Semaine_5/DHT11_UART/.gitignore vendored Normal file
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runs
.vscode
workspace.code-workspace
*.pyc
.idea

210
Semaine_5/DHT11_UART/IP/verilog/dht11_interface.v Normal file
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module dht11_interface (
input wire i_clk, // 27 MHz
inout wire io_dht11_sig,
input wire i_start,
output reg o_dht11_data_ready,
output reg o_busy,
output wire [7:0] o_temp_data,
output wire [7:0] o_hum_data,
output reg o_dht11_error
);
// === DHT11 INTERFACE ===
// === PARAMÈTRES ===
parameter CLK_FREQ = 27_000_000;
localparam T_18MS = CLK_FREQ * 18 / 1000; // cycles pour 18ms
localparam T_80US = CLK_FREQ * 81 / 1_000_000;
localparam T_79US = CLK_FREQ * 79 / 1_000_000;
localparam T_71US = CLK_FREQ * 71 / 1_000_000;
localparam T_51US = CLK_FREQ * 51 / 1_000_000;
localparam T_50US = CLK_FREQ * 50 / 1_000_000;
localparam T_49US = CLK_FREQ * 49 / 1_000_000;
localparam T_40US = CLK_FREQ * 40 / 1_000_000;
localparam T_28US = CLK_FREQ * 28 / 1_000_000;
localparam T_20US = CLK_FREQ * 20 / 1_000_000;
// === Signal bidirectionnel ===
reg sig_dir;
reg sig_out;
wire sig_in;
assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz)
assign sig_in = io_dht11_sig;
// === REGISTRES ===
reg [3:0] state;
reg [31:0] timer;
reg [7:0] temp_data, hum_data;
reg [7:0] temp_dec, hum_dec, checksum;
reg [2:0] bit_count;
reg [5:0] bit_index;
reg [39:0] raw_data;
// === INITIALISATION ===
initial begin
sig_dir = 0;
sig_out = 1;
timer = 0;
state = IDLE;
bit_index = 0;
raw_data = 0;
o_dht11_data_ready = 0;
o_dht11_error = 0;
end
// === FSM ===
localparam IDLE = 4'd0, // Pull up la ligne
START = 4'd1, // Pull low 18ms
WAIT_RESPONSE = 4'd2, // Release la ligne (entre 20 et 40us)
RESPONSE_LOW = 4'd3, // DHT11 pull low 80us
RESPONSE_HIGH = 4'd4, // DHT11 pull high 80us
READ_READ_BITS_LOW = 4'd5,
READ_READ_BITS_HIGH = 4'd6,
DONE = 4'd7,
ERROR = 4'd8;
// === FSM principale ===
always @(posedge i_clk) begin
case (state)
IDLE: begin
sig_dir <= 0;
sig_out <= 1;
timer <= 0;
bit_index <= 0;
raw_data <= 0;
o_busy <= 0;
if (i_start) begin
sig_dir <= 1;
sig_out <= 0;
timer <= 0;
o_busy <= 1;
state <= START;
o_dht11_data_ready <= 0;
o_dht11_error <= 0;
end
end
START: begin
timer <= timer + 1;
if (timer >= T_18MS) begin
sig_dir <= 0; // libérer la ligne
timer <= 0;
state <= WAIT_RESPONSE;
end
end
WAIT_RESPONSE: begin
timer <= timer + 1;
if (sig_in == 0) begin
if (timer > T_20US && timer < T_40US) begin
timer <= 0;
state <= RESPONSE_LOW;
end else begin
state <= ERROR;
end
end else if (timer > T_40US) begin
state <= ERROR;
end
end
RESPONSE_LOW: begin
timer <= timer + 1;
if (sig_in == 1) begin
if (timer > T_79US && timer < T_80US) begin
timer <= 0;
state <= RESPONSE_HIGH;
end else begin
state <= ERROR;
end
end else if (timer > T_80US) begin
state <= ERROR;
end
end
RESPONSE_HIGH: begin
timer <= timer + 1;
if (sig_in == 0) begin
if (timer > T_79US && timer < T_80US) begin
timer <= 0;
state <= READ_BITS_LOW;
end else begin
state <= ERROR;
end
end else if (timer > T_80US) begin
state <= ERROR;
end
end
READ_BITS_LOW: begin
timer <= timer + 1;
if (sig_in == 1) begin
if (timer > T_49US && timer < T_51US) begin
timer <= 0;
state <= READ_BITS_HIGH;
end else begin
state <= ERROR;
end
end else if (timer > T_28US) begin
state <= ERROR;
end
end
READ_BITS_HIGH: begin // entre 26 et 28us = 0 et ~70us = 1
timer <= timer + 1;
if (sig_in == 0) begin
if (timer < T_26US) begin
state <= ERROR;
end
raw_data <= {raw_data[38:0], (timer > T_28US)}; // 1 si high > ~28us
timer <= 0;
bit_index <= bit_index + 1;
if (bit_index == 39) begin // Code a testé ici pour etre sur de capter le dernier bit
state <= DONE;
end else begin
state <= READ_BITS_LOW;
end
end else if (timer > T_71US) begin
state <= ERROR;
end
end
DONE: begin
hum_data <= raw_data[39:32];
hum_dec <= raw_data[31:24];
temp_data <= raw_data[23:16];
temp_dec <= raw_data[15:8];
checksum <= raw_data[7:0];
if (checksum == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin
o_hum_data <= raw_data[39:32];
o_temp_data <= raw_data[23:16];
o_dht11_data_ready <= 1;
end else begin
o_dht11_error <= 1;
end
o_busy <= 0;
state <= IDLE;
end
ERROR: begin
o_dht11_error <= 1;
state <= IDLE;
end
endcase
end
endmodule

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Semaine_5/DHT11_UART/README.md Normal file
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# ULTRASON VIA UART
## Description
This project is designed to control an ultrasonic sensor using UART communication. The ultrasonic sensor is used to measure distance, and the data is transmitted via UART to a connected device.
## Commands
0x01: Start one mesurement of the distance.
0x02: Start continuous mesurement of the distance.
0x03: Stop continuous mesurement of the distance.

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Semaine_5/DHT11_UART/constraints/dht11_uart.cst Normal file
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IO_LOC "tx" 69;
IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "clk" 4;
IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "dht11_sig" 73;
IO_PORT "dht11_sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "leds[0]" 15;
IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" 16;
IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[2]" 17;
IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[3]" 18;
IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[4]" 19;
IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[5]" 20;
IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;

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Semaine_5/DHT11_UART/project.bat Normal file
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@call c:\oss-cad-suite\environment.bat
@echo off
if "%1"=="sim" call scripts\simulate.bat
if "%1"=="wave" call scripts\gtkwave.bat
if "%1"=="clean" call scripts\clean.bat
if "%1"=="build" call scripts\build.bat

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Semaine_5/DHT11_UART/scripts/build.bat Normal file
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@echo off
setlocal
rem === Aller à la racine du projet ===
cd /d %~dp0\..
rem === Config de base ===
set DEVICE=GW2AR-LV18QN88C8/I7
set BOARD=tangnano20k
set TOP=top_uart_ultrason_command
set CST_FILE=%TOP%.cst
set JSON_FILE=runs/%TOP%.json
set PNR_JSON=runs/pnr_%TOP%.json
set BITSTREAM=runs/%TOP%.fs
rem === Créer le dossier runs si nécessaire ===
if not exist runs (
mkdir runs
)
echo === Étape 1 : Synthèse avec Yosys ===
yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
if errorlevel 1 goto error
echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===
nextpnr-himbaechel --json %JSON_FILE% --write %PNR_JSON% --device %DEVICE% --vopt cst=constraints/%CST_FILE% --vopt family=GW2A-18C
if errorlevel 1 goto error
echo === Étape 3 : Packing avec gowin_pack ===
gowin_pack -d %DEVICE% -o %BITSTREAM% %PNR_JSON%
if errorlevel 1 goto error
echo === Étape 4 : Flash avec openFPGALoader ===
openFPGALoader -b %BOARD% %BITSTREAM%
if errorlevel 1 goto error
echo === Compilation et flash réussis ===
goto end
:error
echo === Une erreur est survenue ===
:end
endlocal
pause

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Semaine_5/DHT11_UART/scripts/clean.bat Normal file
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@echo off
echo === Nettoyage du dossier runs ===
rd /s /q runs
mkdir runs

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Semaine_5/DHT11_UART/scripts/gtkwave.bat Normal file
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@echo off
echo === Lancement de GTKWave ===
gtkwave runs/wave.vcd

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Semaine_5/DHT11_UART/scripts/simulate.bat Normal file
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@echo off
echo === Simulation avec Icarus Verilog ===
setlocal enabledelayedexpansion
:: Dossier de sortie
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=dht11_interface
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog
:: Variable pour stocker les fichiers
set FILES=
:: Boucle sur chaque dossier
for %%D in (%DIRS%) do (
for %%F in (%%D\*.v) do (
set FILES=!FILES! %%F
)
)
:: Compilation avec Icarus Verilog
iverilog -g2012 -o %OUT% -s %TOP% %FILES%
endlocal
vvp runs/sim.vvp

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Semaine_5/DHT11_UART/src/verilog/dht11_uart.v Normal file
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module dht11_uart (
input wire i_clk, // 27 MHz
inout wire io_dht11_sig,
input wire i_start,
output wire [7:0] o_leds,
output wire [7:0] o_hum_data,
output reg o_dht11_error
);
// === DHT11 INTERFACE ===
// === PARAMÈTRES ===
parameter CLK_FREQ = 27_000_000;
localparam T_18MS = CLK_FREQ * 18 / 1000; // cycles pour 18ms
localparam T_80US = CLK_FREQ * 81 / 1_000_000;
localparam T_79US = CLK_FREQ * 79 / 1_000_000;
localparam T_71US = CLK_FREQ * 71 / 1_000_000;
localparam T_51US = CLK_FREQ * 51 / 1_000_000;
localparam T_50US = CLK_FREQ * 50 / 1_000_000;
localparam T_49US = CLK_FREQ * 49 / 1_000_000;
localparam T_40US = CLK_FREQ * 40 / 1_000_000;
localparam T_28US = CLK_FREQ * 28 / 1_000_000;
localparam T_20US = CLK_FREQ * 20 / 1_000_000;
// === Signal bidirectionnel ===
reg sig_dir;
reg sig_out;
wire sig_in;
assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz)
assign sig_in = io_dht11_sig;
// === REGISTRES ===
reg [3:0] state;
reg [31:0] timer;
reg [7:0] temp_data, hum_data;
reg [7:0] temp_dec, hum_dec, checksum;
reg [2:0] bit_count;
reg [5:0] bit_index;
reg [39:0] raw_data;
// === INITIALISATION ===
initial begin
sig_dir = 0;
sig_out = 1;
timer = 0;
state = IDLE;
bit_index = 0;
raw_data = 0;
o_dht11_data_ready = 0;
o_dht11_error = 0;
end
// === FSM ===
localparam IDLE = 4'd0, // Pull up la ligne
START = 4'd1, // Pull low 18ms
WAIT_RESPONSE = 4'd2, // Release la ligne (entre 20 et 40us)
RESPONSE_LOW = 4'd3, // DHT11 pull low 80us
RESPONSE_HIGH = 4'd4, // DHT11 pull high 80us
READ_READ_BITS_LOW = 4'd5,
READ_READ_BITS_HIGH = 4'd6,
DONE = 4'd7,
ERROR = 4'd8;
// === FSM principale ===
always @(posedge i_clk) begin
case (state)
IDLE: begin
sig_dir <= 0;
sig_out <= 1;
timer <= 0;
bit_index <= 0;
raw_data <= 0;
o_busy <= 0;
if (i_start) begin
sig_dir <= 1;
sig_out <= 0;
timer <= 0;
o_busy <= 1;
state <= START;
o_dht11_data_ready <= 0;
o_dht11_error <= 0;
end
end
START: begin
timer <= timer + 1;
if (timer >= T_18MS) begin
sig_dir <= 0; // libérer la ligne
timer <= 0;
state <= WAIT_RESPONSE;
end
end
WAIT_RESPONSE: begin
timer <= timer + 1;
if (sig_in == 0) begin
if (timer > T_20US && timer < T_40US) begin
timer <= 0;
state <= RESPONSE_LOW;
end else begin
state <= ERROR;
end
end else if (timer > T_40US) begin
state <= ERROR;
end
end
RESPONSE_LOW: begin
timer <= timer + 1;
if (sig_in == 1) begin
if (timer > T_79US && timer < T_80US) begin
timer <= 0;
state <= RESPONSE_HIGH;
end else begin
state <= ERROR;
end
end else if (timer > T_80US) begin
state <= ERROR;
end
end
RESPONSE_HIGH: begin
timer <= timer + 1;
if (sig_in == 0) begin
if (timer > T_79US && timer < T_80US) begin
timer <= 0;
state <= READ_BITS_LOW;
end else begin
state <= ERROR;
end
end else if (timer > T_80US) begin
state <= ERROR;
end
end
READ_BITS_LOW: begin
timer <= timer + 1;
if (sig_in == 1) begin
if (timer > T_49US && timer < T_51US) begin
timer <= 0;
state <= READ_BITS_HIGH;
end else begin
state <= ERROR;
end
end else if (timer > T_28US) begin
state <= ERROR;
end
end
READ_BITS_HIGH: begin // entre 26 et 28us = 0 et ~70us = 1
timer <= timer + 1;
if (sig_in == 0) begin
if (timer < T_26US) begin
state <= ERROR;
end
raw_data <= {raw_data[38:0], (timer > T_28US)}; // 1 si high > ~28us
timer <= 0;
bit_index <= bit_index + 1;
if (bit_index == 39) begin // Code a testé ici pour etre sur de capter le dernier bit
state <= DONE;
end else begin
state <= READ_BITS_LOW;
end
end else if (timer > T_71US) begin
state <= ERROR;
end
end
DONE: begin
hum_data <= raw_data[39:32];
hum_dec <= raw_data[31:24];
temp_data <= raw_data[23:16];
temp_dec <= raw_data[15:8];
checksum <= raw_data[7:0];
if (checksum == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin
o_hum_data <= raw_data[39:32];
o_temp_data <= raw_data[23:16];
o_dht11_data_ready <= 1;
end else begin
o_dht11_error <= 1;
end
o_busy <= 0;
state <= IDLE;
end
ERROR: begin
o_dht11_error <= 1;
state <= IDLE;
end
endcase
end
endmodule

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Semaine_5/DHT11_UART/tests/verilog/tb_dht11_uart.v Normal file
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`timescale 1ns/1ps
module tb_dht11;
reg clk = 0;
always #18.5 clk = ~clk; // Génère une clock 27 MHz
// === Simulation du module DHT11 ===
// === Module DHT11 INTERFACE ===
// === TEST SEQUENCE ===
initial begin
$dumpfile("runs/wave.vcd");
$dumpvars(0, tb_dht11);
$display("==== Start DHT11 Test ====");
$display("==== End DHT11 Test ====");
$finish;
end
endmodule