forked from tanchou/Verilog
rx fifo et tx fifo on l'air de fonctionner lors des testbenchs
This commit is contained in:
Gamenight77
43
Semaine_4/UART_FIFO/IP/verilog/fifo.v
Normal file
43
Semaine_4/UART_FIFO/IP/verilog/fifo.v
Normal file
@@ -0,0 +1,43 @@
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module fifo #(
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parameter DEPTH = 16,
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parameter WIDTH = 8
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)(
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input wire clk,
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input wire wr_en,
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input wire[WIDTH-1:0] wr_data,
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input wire rd_en,
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output wire[WIDTH-1:0] rd_data,
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output wire full,
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output wire empty
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);
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reg [WIDTH-1:0] fifo[0:DEPTH-1];
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reg [3:0] wr_ptr;
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reg [3:0] rd_ptr;
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reg [3:0] count;
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assign full = (count == DEPTH);
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assign empty = (count == 0);
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assign rd_data = fifo[rd_ptr];
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initial begin
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wr_ptr = 0;
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rd_ptr = 0;
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count = 0;
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end
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always @(posedge clk) begin
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if (wr_en && !full) begin
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fifo[wr_ptr] <= wr_data;
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wr_ptr <= (wr_ptr + 1) % DEPTH;
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count <= count + 1;
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end
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if (rd_en && !empty) begin
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rd_ptr <= (rd_ptr + 1) % DEPTH;
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count <= count - 1;
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end
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end
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endmodule
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143
Semaine_4/UART_FIFO/IP/verilog/other_rx.v
Normal file
143
Semaine_4/UART_FIFO/IP/verilog/other_rx.v
Normal file
@@ -0,0 +1,143 @@
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module other_uart_rx
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#(
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parameter CLK_FRE = 27, //clock frequency(Mhz)
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parameter BAUD_RATE = 115200 //serial baud rate
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)
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(
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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output reg[7:0] rx_data, //received serial data
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output reg rx_data_valid, //received serial data is valid
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input rx_data_ready, //data receiver module ready
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input rx_pin //serial data input
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);
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//calculates the clock cycle for baud rate
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localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE;
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//state machine code
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localparam S_IDLE = 1;
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localparam S_START = 2; //start bit
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localparam S_REC_BYTE = 3; //data bits
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localparam S_STOP = 4; //stop bit
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localparam S_DATA = 5;
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reg[2:0] state;
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reg[2:0] next_state;
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reg rx_d0; //delay 1 clock for rx_pin
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reg rx_d1; //delay 1 clock for rx_d0
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wire rx_negedge; //negedge of rx_pin
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reg[7:0] rx_bits; //temporary storage of received data
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reg[15:0] cycle_cnt; //baud counter
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reg[2:0] bit_cnt; //bit counter
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assign rx_negedge = rx_d1 && ~rx_d0;
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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rx_d0 <= 1'b0;
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rx_d1 <= 1'b0;
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end
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else
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begin
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rx_d0 <= rx_pin;
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rx_d1 <= rx_d0;
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end
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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state <= S_IDLE;
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else
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state <= next_state;
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end
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always@(*)
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begin
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case(state)
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S_IDLE:
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if(rx_negedge)
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next_state <= S_START;
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else
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next_state <= S_IDLE;
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S_START:
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if(cycle_cnt == CYCLE - 1)//one data cycle
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next_state <= S_REC_BYTE;
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else
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next_state <= S_START;
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S_REC_BYTE:
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data
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next_state <= S_STOP;
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else
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next_state <= S_REC_BYTE;
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S_STOP:
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if(cycle_cnt == CYCLE/2 - 1)//half bit cycle,to avoid missing the next byte receiver
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next_state <= S_DATA;
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else
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next_state <= S_STOP;
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S_DATA:
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if(rx_data_ready) //data receive complete
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next_state <= S_IDLE;
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else
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next_state <= S_DATA;
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default:
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next_state <= S_IDLE;
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endcase
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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rx_data_valid <= 1'b0;
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else if(state == S_STOP && next_state != state)
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rx_data_valid <= 1'b1;
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else if(state == S_DATA && rx_data_ready)
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rx_data_valid <= 1'b0;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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rx_data <= 8'd0;
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else if(state == S_STOP && next_state != state)
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rx_data <= rx_bits;//latch received data
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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bit_cnt <= 3'd0;
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end
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else if(state == S_REC_BYTE)
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if(cycle_cnt == CYCLE - 1)
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bit_cnt <= bit_cnt + 3'd1;
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else
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bit_cnt <= bit_cnt;
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else
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bit_cnt <= 3'd0;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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cycle_cnt <= 16'd0;
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else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
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cycle_cnt <= 16'd0;
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else
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cycle_cnt <= cycle_cnt + 16'd1;
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end
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//receive serial data bit data
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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rx_bits <= 8'd0;
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else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
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rx_bits[bit_cnt] <= rx_pin;
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else
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rx_bits <= rx_bits;
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end
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endmodule
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133
Semaine_4/UART_FIFO/IP/verilog/other_tx.v
Normal file
133
Semaine_4/UART_FIFO/IP/verilog/other_tx.v
Normal file
@@ -0,0 +1,133 @@
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module other_uart_tx
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#(
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parameter CLK_FRE = 27, //clock frequency(Mhz)
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parameter BAUD_RATE = 115200 //serial baud rate
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)
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(
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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input[7:0] tx_data, //data to send
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input tx_data_valid, //data to be sent is valid
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output reg tx_data_ready, //send ready
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output tx_pin //serial data output
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);
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//calculates the clock cycle for baud rate
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localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE;
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//state machine code
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localparam S_IDLE = 1;
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localparam S_START = 2;//start bit
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localparam S_SEND_BYTE = 3;//data bits
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localparam S_STOP = 4;//stop bit
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reg[2:0] state;
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reg[2:0] next_state;
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reg[15:0] cycle_cnt; //baud counter
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reg[2:0] bit_cnt;//bit counter
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reg[7:0] tx_data_latch; //latch data to send
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reg tx_reg; //serial data output
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assign tx_pin = tx_reg;
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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state <= S_IDLE;
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else
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state <= next_state;
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end
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always@(*)
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begin
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case(state)
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S_IDLE:
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if(tx_data_valid == 1'b1)
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next_state <= S_START;
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else
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next_state <= S_IDLE;
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S_START:
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if(cycle_cnt == CYCLE - 1)
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next_state <= S_SEND_BYTE;
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else
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next_state <= S_START;
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S_SEND_BYTE:
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
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next_state <= S_STOP;
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else
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next_state <= S_SEND_BYTE;
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S_STOP:
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if(cycle_cnt == CYCLE - 1)
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next_state <= S_IDLE;
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else
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next_state <= S_STOP;
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default:
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next_state <= S_IDLE;
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endcase
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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tx_data_ready <= 1'b0;
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end
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else if(state == S_IDLE)
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if(tx_data_valid == 1'b1)
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tx_data_ready <= 1'b0;
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else
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tx_data_ready <= 1'b1;
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else if(state == S_STOP && cycle_cnt == CYCLE - 1)
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tx_data_ready <= 1'b1;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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tx_data_latch <= 8'd0;
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end
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else if(state == S_IDLE && tx_data_valid == 1'b1)
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tx_data_latch <= tx_data;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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bit_cnt <= 3'd0;
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end
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else if(state == S_SEND_BYTE)
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if(cycle_cnt == CYCLE - 1)
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bit_cnt <= bit_cnt + 3'd1;
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else
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bit_cnt <= bit_cnt;
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else
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bit_cnt <= 3'd0;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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cycle_cnt <= 16'd0;
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else if((state == S_SEND_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
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cycle_cnt <= 16'd0;
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else
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cycle_cnt <= cycle_cnt + 16'd1;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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tx_reg <= 1'b1;
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else
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case(state)
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S_IDLE,S_STOP:
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tx_reg <= 1'b1;
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S_START:
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tx_reg <= 1'b0;
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S_SEND_BYTE:
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tx_reg <= tx_data_latch[bit_cnt];
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default:
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tx_reg <= 1'b1;
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endcase
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end
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endmodule
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145
Semaine_4/UART_FIFO/IP/verilog/uart_rx.v
Normal file
145
Semaine_4/UART_FIFO/IP/verilog/uart_rx.v
Normal file
@@ -0,0 +1,145 @@
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module uart_rx #(
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parameter CLK_FREQ = 27_000_000,
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parameter BAUD_RATE = 115200
|
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)(
|
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input clk, //clock input
|
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input rst_p, //asynchronous reset input, high active
|
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input rx_enable, //data receiver module ready
|
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input rx_pin, //serial data input
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output reg[7:0] rx_data, //received serial data
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output reg rx_received //received serial data is valid
|
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);
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localparam CYCLE = CLK_FREQ / BAUD_RATE;
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//state machine code
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localparam S_IDLE = 1;
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localparam S_START = 2; //start bit
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localparam S_REC_BYTE = 3; //data bits
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localparam S_STOP = 4; //stop bit
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localparam S_DATA = 5;
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reg[2:0] state;
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reg[2:0] next_state;
|
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reg rx_d0; //delay 1 clock for rx_pin
|
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reg rx_d1; //delay 1 clock for rx_d0
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wire rx_negedge; //negedge of rx_pin
|
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reg[7:0] rx_bits; //temporary storage of received data
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||||
reg[15:0] cycle_cnt; //baud counter
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reg[2:0] bit_cnt; //bit counter
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assign rx_negedge = rx_d1 && ~rx_d0; // Front déscendant
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always@(posedge clk or posedge rst_p) // Filtrage du signial
|
||||
begin
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if(rst_p == 1'b1)begin
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rx_d0 <= 1'b0;
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rx_d1 <= 1'b0;
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end else begin
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||||
rx_d0 <= rx_pin;
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rx_d1 <= rx_d0;
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end
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end
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always@(posedge clk or posedge rst_p)begin // Compteur d'etat
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if(rst_p == 1'b1)
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state <= S_IDLE;
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else
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state <= next_state;
|
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end
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|
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always@(*)begin
|
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case(state)
|
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S_IDLE:
|
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if(rx_negedge) // Detection du start bit
|
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next_state = S_START;
|
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else
|
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next_state = S_IDLE;
|
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|
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S_START:
|
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if(cycle_cnt == CYCLE - 1) //one data cycle
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next_state = S_REC_BYTE;
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else
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next_state = S_START;
|
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|
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S_REC_BYTE:
|
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data
|
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next_state = S_STOP;
|
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else
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next_state = S_REC_BYTE;
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|
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S_STOP:
|
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if(cycle_cnt == CYCLE/2 - 1) //half bit cycle,to avoid missing the next byte receiver
|
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next_state = S_DATA;
|
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else
|
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next_state = S_STOP;
|
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|
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S_DATA:
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if(rx_enable) //data receive complete
|
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next_state = S_IDLE;
|
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else
|
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next_state = S_DATA;
|
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|
||||
default:
|
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next_state = S_IDLE;
|
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endcase
|
||||
end
|
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|
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always@(posedge clk or posedge rst_p)
|
||||
begin
|
||||
if(rst_p == 1'b1)
|
||||
rx_received <= 1'b0;
|
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else if(state == S_STOP && next_state != state)
|
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rx_received <= 1'b1;
|
||||
else if(state == S_DATA && rx_enable)
|
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rx_received <= 1'b0;
|
||||
end
|
||||
|
||||
always@(posedge clk or posedge rst_p)
|
||||
begin
|
||||
if(rst_p == 1'b1)
|
||||
rx_data <= 8'd0;
|
||||
else if(state == S_STOP && next_state != state)
|
||||
rx_data <= rx_bits;//latch received data
|
||||
end
|
||||
|
||||
always@(posedge clk or posedge rst_p)
|
||||
begin
|
||||
if(rst_p == 1'b1)
|
||||
begin
|
||||
bit_cnt <= 3'd0;
|
||||
end
|
||||
else if(state == S_REC_BYTE)
|
||||
if(cycle_cnt == CYCLE - 1)
|
||||
bit_cnt <= bit_cnt + 3'd1;
|
||||
else
|
||||
bit_cnt <= bit_cnt;
|
||||
else
|
||||
bit_cnt <= 3'd0;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or posedge rst_p)
|
||||
begin
|
||||
if(rst_p == 1'b1)
|
||||
cycle_cnt <= 16'd0;
|
||||
else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
|
||||
cycle_cnt <= 16'd0;
|
||||
else
|
||||
cycle_cnt <= cycle_cnt + 16'd1;
|
||||
end
|
||||
//receive serial data bit data
|
||||
always@(posedge clk or posedge rst_p)
|
||||
begin
|
||||
if(rst_p == 1'b1)
|
||||
rx_bits <= 8'd0;
|
||||
else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
|
||||
rx_bits[bit_cnt] <= rx_pin;
|
||||
else
|
||||
rx_bits <= rx_bits;
|
||||
end
|
||||
endmodule
|
||||
131
Semaine_4/UART_FIFO/IP/verilog/uart_tx.v
Normal file
131
Semaine_4/UART_FIFO/IP/verilog/uart_tx.v
Normal file
@@ -0,0 +1,131 @@
|
||||
module uart_tx #(
|
||||
parameter CLK_FREQ = 27_000_000,
|
||||
parameter BAUD_RATE = 115200
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst_p,
|
||||
input wire[7:0] data,
|
||||
input wire tx_enable,
|
||||
|
||||
output reg tx_ready,
|
||||
output wire tx
|
||||
);
|
||||
|
||||
localparam CYCLE = CLK_FREQ / BAUD_RATE;
|
||||
|
||||
localparam IDLE = 2'd0;
|
||||
localparam START = 2'd1;
|
||||
localparam DATA = 2'd2;
|
||||
localparam STOP = 2'd3;
|
||||
|
||||
reg [1:0] state = IDLE;
|
||||
reg [1:0] next_state;
|
||||
reg [15:0] cycle_cnt; //baud counter
|
||||
reg tx_reg;
|
||||
reg [2:0] bit_cnt;
|
||||
reg [7:0] tx_data_latch = 0;
|
||||
|
||||
|
||||
assign tx = tx_reg;
|
||||
|
||||
always@(posedge clk or posedge rst_p)begin // Avance d'etat
|
||||
if(rst_p == 1'b1)
|
||||
state <= IDLE;
|
||||
else
|
||||
state <= next_state;
|
||||
end
|
||||
|
||||
always@(*) begin
|
||||
case(state)
|
||||
IDLE:
|
||||
if(tx_enable == 1'b1)
|
||||
next_state = START;
|
||||
else
|
||||
next_state = IDLE;
|
||||
|
||||
START:
|
||||
if(cycle_cnt == CYCLE - 1)
|
||||
next_state = DATA;
|
||||
else
|
||||
next_state = START;
|
||||
|
||||
DATA:
|
||||
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
|
||||
next_state = STOP;
|
||||
else
|
||||
next_state = DATA;
|
||||
|
||||
STOP:
|
||||
if(cycle_cnt == CYCLE - 1)
|
||||
next_state = IDLE;
|
||||
else
|
||||
next_state = STOP;
|
||||
default:
|
||||
next_state = IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
always@(posedge clk or posedge rst_p)begin // tx_ready block
|
||||
if(rst_p == 1'b1)
|
||||
tx_ready <= 1'b0; // Reset
|
||||
else if(state == IDLE && tx_enable == 1'b1)
|
||||
tx_ready <= 1'b0; // Pas prêt tant que les données sont valides
|
||||
else if(state == IDLE)
|
||||
tx_ready <= 1'b1;
|
||||
else if(state == STOP && cycle_cnt == CYCLE - 1)
|
||||
tx_ready <= 1'b1; // Prêt une fois le bit STOP envoyé
|
||||
else
|
||||
tx_ready <= tx_ready; // Reste inchangé dans d'autres cas
|
||||
end
|
||||
|
||||
|
||||
|
||||
always@(posedge clk or posedge rst_p) begin // tx_data_latch block
|
||||
if(rst_p == 1'b1) begin
|
||||
tx_data_latch <= 8'd0;
|
||||
end else if(state == IDLE && tx_enable == 1'b1) begin
|
||||
tx_data_latch <= data; // Charger les données de data dans tx_data_latch
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or posedge rst_p)begin // DATA bit_cnt block
|
||||
if(rst_p == 1'b1)begin
|
||||
bit_cnt <= 3'd0;
|
||||
|
||||
end else if(state == DATA)
|
||||
if(cycle_cnt == CYCLE - 1)
|
||||
bit_cnt <= bit_cnt + 3'd1;
|
||||
else
|
||||
bit_cnt <= bit_cnt;
|
||||
else
|
||||
bit_cnt <= 3'd0;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or posedge rst_p)begin // Cycle counter
|
||||
if(rst_p == 1'b1)
|
||||
cycle_cnt <= 16'd0;
|
||||
|
||||
else if((state == DATA && cycle_cnt == CYCLE - 1) || next_state != state)
|
||||
cycle_cnt <= 16'd0;
|
||||
else
|
||||
cycle_cnt <= cycle_cnt + 16'd1;
|
||||
end
|
||||
|
||||
always@(posedge clk or posedge rst_p)begin // tx state managment
|
||||
if(rst_p == 1'b1)
|
||||
tx_reg <= 1'b1;
|
||||
else
|
||||
case(state)
|
||||
IDLE,STOP:
|
||||
tx_reg <= 1'b1;
|
||||
START:
|
||||
tx_reg <= 1'b0;
|
||||
DATA:
|
||||
tx_reg <= tx_data_latch[bit_cnt]; // SENDING BYTE HERE
|
||||
default:
|
||||
tx_reg <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
Reference in New Issue
Block a user