rx fifo et tx fifo on l'air de fonctionner lors des testbenchs

Semaine_4/UART_FIFO/IP/verilog/fifo.v

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+ module fifo #(
+	parameter       DEPTH = 16,
+	parameter       WIDTH = 8
+)(
+    input wire              clk,
+    input wire              wr_en,
+    input wire[WIDTH-1:0]   wr_data,
+    input wire              rd_en,
+    output wire[WIDTH-1:0]  rd_data,
+
+    output wire             full,
+    output wire             empty
+);
+
+    reg [WIDTH-1:0]         fifo[0:DEPTH-1];
+    reg [3:0]               wr_ptr;
+    reg [3:0]               rd_ptr;
+    reg [3:0]               count;
+
+    assign full = (count == DEPTH);
+    assign empty = (count == 0);
+    assign rd_data = fifo[rd_ptr];
+
+    initial begin
+        wr_ptr = 0;
+        rd_ptr = 0;
+        count = 0;
+    end
+
+    always @(posedge clk) begin
+        if (wr_en && !full) begin
+            fifo[wr_ptr] <= wr_data;
+            wr_ptr <= (wr_ptr + 1) % DEPTH;
+            count <= count + 1;
+        end
+
+        if (rd_en && !empty) begin
+            rd_ptr <= (rd_ptr + 1) % DEPTH;
+            count <= count - 1;
+        end
+    end
+    
+endmodule