forked from tanchou/Verilog
rx fifo et tx fifo on l'air de fonctionner lors des testbenchs
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133
Semaine_4/UART_FIFO/IP/verilog/other_tx.v
Normal file
133
Semaine_4/UART_FIFO/IP/verilog/other_tx.v
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module other_uart_tx
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#(
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parameter CLK_FRE = 27, //clock frequency(Mhz)
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parameter BAUD_RATE = 115200 //serial baud rate
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)
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(
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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input[7:0] tx_data, //data to send
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input tx_data_valid, //data to be sent is valid
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output reg tx_data_ready, //send ready
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output tx_pin //serial data output
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);
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//calculates the clock cycle for baud rate
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localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE;
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//state machine code
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localparam S_IDLE = 1;
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localparam S_START = 2;//start bit
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localparam S_SEND_BYTE = 3;//data bits
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localparam S_STOP = 4;//stop bit
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reg[2:0] state;
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reg[2:0] next_state;
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reg[15:0] cycle_cnt; //baud counter
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reg[2:0] bit_cnt;//bit counter
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reg[7:0] tx_data_latch; //latch data to send
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reg tx_reg; //serial data output
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assign tx_pin = tx_reg;
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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state <= S_IDLE;
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else
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state <= next_state;
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end
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always@(*)
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begin
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case(state)
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S_IDLE:
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if(tx_data_valid == 1'b1)
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next_state <= S_START;
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else
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next_state <= S_IDLE;
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S_START:
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if(cycle_cnt == CYCLE - 1)
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next_state <= S_SEND_BYTE;
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else
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next_state <= S_START;
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S_SEND_BYTE:
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
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next_state <= S_STOP;
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else
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next_state <= S_SEND_BYTE;
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S_STOP:
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if(cycle_cnt == CYCLE - 1)
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next_state <= S_IDLE;
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else
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next_state <= S_STOP;
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default:
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next_state <= S_IDLE;
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endcase
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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tx_data_ready <= 1'b0;
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end
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else if(state == S_IDLE)
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if(tx_data_valid == 1'b1)
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tx_data_ready <= 1'b0;
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else
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tx_data_ready <= 1'b1;
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else if(state == S_STOP && cycle_cnt == CYCLE - 1)
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tx_data_ready <= 1'b1;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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tx_data_latch <= 8'd0;
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end
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else if(state == S_IDLE && tx_data_valid == 1'b1)
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tx_data_latch <= tx_data;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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bit_cnt <= 3'd0;
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end
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else if(state == S_SEND_BYTE)
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if(cycle_cnt == CYCLE - 1)
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bit_cnt <= bit_cnt + 3'd1;
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else
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bit_cnt <= bit_cnt;
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else
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bit_cnt <= 3'd0;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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cycle_cnt <= 16'd0;
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else if((state == S_SEND_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
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cycle_cnt <= 16'd0;
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else
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cycle_cnt <= cycle_cnt + 16'd1;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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tx_reg <= 1'b1;
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else
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case(state)
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S_IDLE,S_STOP:
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tx_reg <= 1'b1;
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S_START:
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tx_reg <= 1'b0;
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S_SEND_BYTE:
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tx_reg <= tx_data_latch[bit_cnt];
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default:
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tx_reg <= 1'b1;
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endcase
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end
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endmodule
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