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rx fifo et tx fifo on l'air de fonctionner lors des testbenchs

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Gamenight77
2025-05-06 10:59:08 +02:00
parent 1ca3456ab8
commit 86d4f5ddd2
11 changed files with 799 additions and 306 deletions
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Semaine_4/UART_FIFO/scripts/simulate.bat
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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=tb_uart
set TOP=tb_uart_tx_fifo
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog