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rx fifo et tx fifo on l'air de fonctionner lors des testbenchs

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Gamenight77
2025-05-06 10:59:08 +02:00
parent 1ca3456ab8
commit 86d4f5ddd2
11 changed files with 799 additions and 306 deletions
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189
Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v
View File

@@ -1,145 +1,68 @@
module uart_rx #(
module uart_rx_fifo #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200
parameter BAUD_RATE = 115200,
parameter FIFO_DEPTH = 8
)(
input clk, //clock input
input rst_p, //asynchronous reset input, high active
input rx_enable, //data receiver module ready
input rx_pin, //serial data input
output reg[7:0] rx_data, //received serial data
output reg rx_received //received serial data is valid
input clk,
input rd_en,
output reg [7:0] rd_data,
input rx_pin,
output data_available
);
localparam CYCLE = CLK_FREQ / BAUD_RATE;
//state machine code
localparam S_IDLE = 1;
localparam S_START = 2; //start bit
localparam S_REC_BYTE = 3; //data bits
localparam S_STOP = 4; //stop bit
localparam S_DATA = 5;
// UART RX wires
wire [7:0] rx_data;
wire rx_received;
reg[2:0] state;
reg[2:0] next_state;
// FIFO control
reg wr_en;
wire fifo_empty;
wire fifo_full;
wire [7:0] fifo_rd_data;
reg rx_d0; //delay 1 clock for rx_pin
reg rx_d1; //delay 1 clock for rx_d0
wire rx_negedge; //negedge of rx_pin
reg[7:0] rx_bits; //temporary storage of received data
reg[15:0] cycle_cnt; //baud counter
reg[2:0] bit_cnt; //bit counter
// UART Receiver instance
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) uart_rx_inst (
.clk(clk),
.rst_p(1'b0),
.rx_enable(1'b1),
.rx_pin(rx_pin),
.rx_data(rx_data),
.rx_received(rx_received)
);
assign rx_negedge = rx_d1 && ~rx_d0; // Front déscendant
// FIFO instance
fifo #(
.WIDTH(8),
.DEPTH(FIFO_DEPTH)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),
.wr_data(rx_data),
.rd_en(rd_en),
.rd_data(fifo_rd_data),
.empty(fifo_empty),
.full(fifo_full)
);
always@(posedge clk or posedge rst_p) // Filtrage du signial
begin
if(rst_p == 1'b1)begin
rx_d0 <= 1'b0;
rx_d1 <= 1'b0;
end else begin
rx_d0 <= rx_pin;
rx_d1 <= rx_d0;
end
end
assign data_available = ~fifo_empty;
always@(posedge clk or posedge rst_p)begin // Compteur d'etat
if(rst_p == 1'b1)
state <= S_IDLE;
else
state <= next_state;
end
always@(*)begin
case(state)
S_IDLE:
if(rx_negedge) // Detection du start bit
next_state = S_START;
else
next_state = S_IDLE;
S_START:
if(cycle_cnt == CYCLE - 1) //one data cycle
next_state = S_REC_BYTE;
else
next_state = S_START;
S_REC_BYTE:
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data
next_state = S_STOP;
else
next_state = S_REC_BYTE;
S_STOP:
if(cycle_cnt == CYCLE/2 - 1) //half bit cycle,to avoid missing the next byte receiver
next_state = S_DATA;
else
next_state = S_STOP;
S_DATA:
if(rx_enable) //data receive complete
next_state = S_IDLE;
else
next_state = S_DATA;
default:
next_state = S_IDLE;
endcase
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
rx_received <= 1'b0;
else if(state == S_STOP && next_state != state)
rx_received <= 1'b1;
else if(state == S_DATA && rx_enable)
rx_received <= 1'b0;
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
rx_data <= 8'd0;
else if(state == S_STOP && next_state != state)
rx_data <= rx_bits;//latch received data
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
begin
bit_cnt <= 3'd0;
// Enregistrement explicite des données lues pour stabilité
always @(posedge clk) begin
if (rd_en && !fifo_empty) begin
rd_data <= fifo_rd_data;
end
else if(state == S_REC_BYTE)
if(cycle_cnt == CYCLE - 1)
bit_cnt <= bit_cnt + 3'd1;
else
bit_cnt <= bit_cnt;
else
bit_cnt <= 3'd0;
end
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
cycle_cnt <= 16'd0;
else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
cycle_cnt <= 16'd0;
else
cycle_cnt <= cycle_cnt + 16'd1;
end
//receive serial data bit data
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
rx_bits <= 8'd0;
else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
rx_bits[bit_cnt] <= rx_pin;
else
rx_bits <= rx_bits;
end
// Écriture dans la FIFO uniquement si donnée reçue ET FIFO pas pleine
always @(posedge clk) begin
if (rx_received && !fifo_full) begin
wr_en <= 1'b1;
end else begin
wr_en <= 1'b0;
end
end
endmodule

187
Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v
View File

@@ -1,131 +1,86 @@
module uart_tx #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200
module uart_tx_fifo #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200,
parameter FIFO_DEPTH = 8
)(
input wire clk,
input wire rst_p,
input wire[7:0] data,
input wire tx_enable,
output reg tx_ready,
output wire tx
input clk,
input wr_en,
input [7:0] wr_data,
output tx_pin,
output fifo_full
);
localparam CYCLE = CLK_FREQ / BAUD_RATE;
// FIFO wires
wire [7:0] fifo_rd_data;
wire fifo_empty;
reg fifo_rd_en;
localparam IDLE = 2'd0;
localparam START = 2'd1;
localparam DATA = 2'd2;
localparam STOP = 2'd3;
// UART wires
wire tx_ready;
reg uart_tx_enable;
reg [7:0] uart_tx_data;
reg [1:0] state = IDLE;
reg [1:0] next_state;
reg [15:0] cycle_cnt; //baud counter
reg tx_reg;
reg [2:0] bit_cnt;
reg [7:0] tx_data_latch = 0;
// FSM
typedef enum logic [1:0] {
IDLE,
WAIT_READY,
SEND
} state_t;
state_t state = IDLE;
assign tx = tx_reg;
// FIFO instantiation
fifo #(
.WIDTH(8),
.DEPTH(FIFO_DEPTH)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),
.wr_data(wr_data),
.rd_en(fifo_rd_en),
.rd_data(fifo_rd_data),
.empty(fifo_empty),
.full(fifo_full)
);
always@(posedge clk or posedge rst_p)begin // Avance d'etat
if(rst_p == 1'b1)
state <= IDLE;
else
state <= next_state;
end
// UART TX instantiation
uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) uart_tx_inst (
.clk(clk),
.rst_p(1'b0),
.data(uart_tx_data),
.tx_enable(uart_tx_enable),
.tx_ready(tx_ready),
.tx(tx_pin)
);
always@(*) begin
case(state)
IDLE:
if(tx_enable == 1'b1)
next_state = START;
else
next_state = IDLE;
always_ff @(posedge clk) begin
// Valeurs par défaut
fifo_rd_en <= 0;
uart_tx_enable <= 0;
START:
if(cycle_cnt == CYCLE - 1)
next_state = DATA;
else
next_state = START;
case (state)
IDLE: begin
if (!fifo_empty) begin
state <= WAIT_READY;
end
end
DATA:
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
next_state = STOP;
else
next_state = DATA;
WAIT_READY: begin
if (tx_ready) begin
fifo_rd_en <= 1;
state <= SEND;
end
end
STOP:
if(cycle_cnt == CYCLE - 1)
next_state = IDLE;
else
next_state = STOP;
default:
next_state = IDLE;
SEND: begin
uart_tx_data <= fifo_rd_data;
uart_tx_enable <= 1;
state <= IDLE;
end
endcase
end
always@(posedge clk or posedge rst_p)begin // tx_ready block
if(rst_p == 1'b1)
tx_ready <= 1'b0; // Reset
else if(state == IDLE && tx_enable == 1'b1)
tx_ready <= 1'b0; // Pas prêt tant que les données sont valides
else if(state == IDLE)
tx_ready <= 1'b1;
else if(state == STOP && cycle_cnt == CYCLE - 1)
tx_ready <= 1'b1; // Prêt une fois le bit STOP envoyé
else
tx_ready <= tx_ready; // Reste inchangé dans d'autres cas
end
always@(posedge clk or posedge rst_p) begin // tx_data_latch block
if(rst_p == 1'b1) begin
tx_data_latch <= 8'd0;
end else if(state == IDLE && tx_enable == 1'b1) begin
tx_data_latch <= data; // Charger les données de `data` dans `tx_data_latch`
end
end
always@(posedge clk or posedge rst_p)begin // DATA bit_cnt block
if(rst_p == 1'b1)begin
bit_cnt <= 3'd0;
end else if(state == DATA)
if(cycle_cnt == CYCLE - 1)
bit_cnt <= bit_cnt + 3'd1;
else
bit_cnt <= bit_cnt;
else
bit_cnt <= 3'd0;
end
always@(posedge clk or posedge rst_p)begin // Cycle counter
if(rst_p == 1'b1)
cycle_cnt <= 16'd0;
else if((state == DATA && cycle_cnt == CYCLE - 1) || next_state != state)
cycle_cnt <= 16'd0;
else
cycle_cnt <= cycle_cnt + 16'd1;
end
always@(posedge clk or posedge rst_p)begin // tx state managment
if(rst_p == 1'b1)
tx_reg <= 1'b1;
else
case(state)
IDLE,STOP:
tx_reg <= 1'b1;
START:
tx_reg <= 1'b0;
DATA:
tx_reg <= tx_data_latch[bit_cnt]; // SENDING BYTE HERE
default:
tx_reg <= 1'b1;
endcase
end
endmodule
endmodule