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rx fifo et tx fifo on l'air de fonctionner lors des testbenchs

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This commit is contained in:
Gamenight77
2025-05-06 10:59:08 +02:00
parent 1ca3456ab8
commit 86d4f5ddd2
11 changed files with 799 additions and 306 deletions
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60
Semaine_4/UART_FIFO/tests/verilog/tb_uart_rx_fifo.v
View File

@@ -1,6 +1,6 @@
`timescale 1ns / 1ps
module tb_uart_rx;
module tb_uart_rx_fifo;
reg clk = 0;
reg rx;
@@ -10,8 +10,8 @@ module tb_uart_rx;
reg tx_data_valid;
reg tx_data_ready;
reg rx_received;
wire rx_enable = 1'b1; // Enable the receiver
reg rd_en;
wire data_available;
localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200;
@@ -27,23 +27,24 @@ module tb_uart_rx;
.rst_n(1'b1)
);
uart_rx #(
uart_rx_fifo #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) rx_instance (
.BAUD_RATE(BAUD_RATE),
.FIFO_DEPTH(8)
) rx_fifo_instance (
.clk(clk),
.rx_pin(rx),
.rx_data(data_out),
.rx_received(rx_received),
.rx_enable(rx_enable)
.rd_en(rd_en),
.rd_data(data_out),
.data_available(data_available)
);
always #(CLK_PERIOD_NS/2) clk = ~clk;
initial begin
$dumpfile("runs/uart_rx.vcd");
$dumpvars(0, tb_uart_rx);
$display("======== Start UART RX test =========");
$dumpfile("runs/uart_rx_fifo.vcd");
$dumpvars(0, tb_uart_rx_fifo);
$display("======== Start UART RX FIFO test =========");
#100;
data_in = 8'd123; // Data to send
@@ -56,12 +57,41 @@ module tb_uart_rx;
tx_data_valid = 1'b0; // Clear the valid signal
wait(rx_received); // Wait for the receiver to receive the data
data_in = 8'd234; // Data to send
wait(tx_data_ready); // Wait for the transmitter to be ready
#1; // Small delay to ensure the data is latched
$display("Data sent: %d", data_in);
tx_data_valid = 1'b1; // Indicate that the data is valid
wait(tx_data_ready == 0);
tx_data_valid = 1'b0; // Clear the valid signal
data_in = 8'd101; // Data to send
wait(tx_data_ready); // Wait for the transmitter to be ready
#1; // Small delay to ensure the data is latched
tx_data_valid = 1'b1; // Indicate that the data is valid
wait(tx_data_ready == 0);
tx_data_valid = 1'b0; // Clear the valid signal
wait(data_available); // Wait for the receiver to receive the data
rd_en = 1'b1; // Enable read from FIFO
#37; // Small delay to ensure the data is read
$display("Data received: %d", data_out); // Display the received data
rd_en = 1'b0; // Disable read from FIFO
#37; // Small delay to ensure the data is read
$display("======== END UART RX test =========");
rd_en = 1'b1; // Enable read from FIFO
#37; // Small delay to ensure the data is read
$display("Data received: %d", data_out); // Display the received data
rd_en = 1'b0; // Disable read from FIFO
#37; // Small delay to ensure the data is read
$display("======== END UART RX FIFO test =========");
$finish;
end
endmodule

70
Semaine_4/UART_FIFO/tests/verilog/tb_uart_tx_fifo.v
View File

@@ -1,16 +1,17 @@
`timescale 1ns/1ps
module tb_uart_tx;
module tb_uart_tx_fifo;
reg clk = 0;
reg tx_enable = 0;
reg [7:0] data_in = 8'h00;
reg [7:0] data_out;
wire tx;
reg tx_ready;
wire rx_recieved;
wire fifo_full;
reg wr_en = 0;
always #18.5 clk = ~clk;
other_uart_rx rx_instance(
@@ -22,55 +23,44 @@ module tb_uart_tx;
.rx_data_ready(1'b1)
);
uart_tx #(
uart_tx_fifo #(
.CLK_FREQ(27_000_000),
.BAUD_RATE(115_200)
)tx_instance (
.BAUD_RATE(115_200),
.FIFO_DEPTH(8)
)tx_fifo_instance (
.clk(clk),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.data(data_in),
.tx(tx),
.rst_p(1'b0)
.wr_en(wr_en),
.wr_data(data_in),
.tx_pin(tx),
.fifo_full(fifo_full)
);
initial begin
$dumpfile("runs/uart_tx.vcd");
$dumpvars(0, tb_uart_tx);
$dumpfile("runs/uart_tx_fifo.vcd");
$dumpvars(0, tb_uart_tx_fifo);
$display("======== Start UART TX test =========");
$display("======== Start UART TX FIFO test =========");
#100;
#50;
data_in <= 8'd234; // 234
tx_enable <= 1;
wait(tx_ready == 1'b0);
tx_enable <= 0;
data_in <= 8'd234;
wr_en <= 1'b1; // Activer l'écriture dans la FIFO
#37;
wr_en <= 1'b0; // Désactiver l'écriture dans la FIFO
// Attendre
wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif
data_in <= 8'd123;
wr_en <= 1'b1; // Activer l'écriture dans la FIFO
#37;
wr_en <= 1'b0; // Désactiver l'écriture dans la FIFO
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
data_in <= 8'd45;
wr_en <= 1'b1; // Activer l'écriture dans la FIFO
#37;
wr_en <= 1'b0; // Désactiver l'écriture dans la FIFO
#1000;
$display("======== END UART TX FIFO test =========");
wait(tx_ready == 1'b1); // Attendre que le signal de reception soit actif
data_in <= 8'd202; // 202
tx_enable <= 1;
wait(tx_ready == 1'b0);
tx_enable <= 0;
// Attendre
wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
$display("======== END UART TX test =========");
#1000;
#1000000;
$stop;
end