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rx fifo et tx fifo on l'air de fonctionner lors des testbenchs

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This commit is contained in:
Gamenight77
2025-05-06 10:59:08 +02:00
parent 1ca3456ab8
commit 86d4f5ddd2
11 changed files with 799 additions and 306 deletions
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43
Semaine_4/UART_FIFO/IP/verilog/fifo.v Normal file
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module fifo #(
parameter DEPTH = 16,
parameter WIDTH = 8
)(
input wire clk,
input wire wr_en,
input wire[WIDTH-1:0] wr_data,
input wire rd_en,
output wire[WIDTH-1:0] rd_data,
output wire full,
output wire empty
);
reg [WIDTH-1:0] fifo[0:DEPTH-1];
reg [3:0] wr_ptr;
reg [3:0] rd_ptr;
reg [3:0] count;
assign full = (count == DEPTH);
assign empty = (count == 0);
assign rd_data = fifo[rd_ptr];
initial begin
wr_ptr = 0;
rd_ptr = 0;
count = 0;
end
always @(posedge clk) begin
if (wr_en && !full) begin
fifo[wr_ptr] <= wr_data;
wr_ptr <= (wr_ptr + 1) % DEPTH;
count <= count + 1;
end
if (rd_en && !empty) begin
rd_ptr <= (rd_ptr + 1) % DEPTH;
count <= count - 1;
end
end
endmodule

143
Semaine_4/UART_FIFO/IP/verilog/other_rx.v Normal file
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module other_uart_rx
#(
parameter CLK_FRE = 27, //clock frequency(Mhz)
parameter BAUD_RATE = 115200 //serial baud rate
)
(
input clk, //clock input
input rst_n, //asynchronous reset input, low active
output reg[7:0] rx_data, //received serial data
output reg rx_data_valid, //received serial data is valid
input rx_data_ready, //data receiver module ready
input rx_pin //serial data input
);
//calculates the clock cycle for baud rate
localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE;
//state machine code
localparam S_IDLE = 1;
localparam S_START = 2; //start bit
localparam S_REC_BYTE = 3; //data bits
localparam S_STOP = 4; //stop bit
localparam S_DATA = 5;
reg[2:0] state;
reg[2:0] next_state;
reg rx_d0; //delay 1 clock for rx_pin
reg rx_d1; //delay 1 clock for rx_d0
wire rx_negedge; //negedge of rx_pin
reg[7:0] rx_bits; //temporary storage of received data
reg[15:0] cycle_cnt; //baud counter
reg[2:0] bit_cnt; //bit counter
assign rx_negedge = rx_d1 && ~rx_d0;
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
begin
rx_d0 <= 1'b0;
rx_d1 <= 1'b0;
end
else
begin
rx_d0 <= rx_pin;
rx_d1 <= rx_d0;
end
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
state <= S_IDLE;
else
state <= next_state;
end
always@(*)
begin
case(state)
S_IDLE:
if(rx_negedge)
next_state <= S_START;
else
next_state <= S_IDLE;
S_START:
if(cycle_cnt == CYCLE - 1)//one data cycle
next_state <= S_REC_BYTE;
else
next_state <= S_START;
S_REC_BYTE:
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data
next_state <= S_STOP;
else
next_state <= S_REC_BYTE;
S_STOP:
if(cycle_cnt == CYCLE/2 - 1)//half bit cycle,to avoid missing the next byte receiver
next_state <= S_DATA;
else
next_state <= S_STOP;
S_DATA:
if(rx_data_ready) //data receive complete
next_state <= S_IDLE;
else
next_state <= S_DATA;
default:
next_state <= S_IDLE;
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
rx_data_valid <= 1'b0;
else if(state == S_STOP && next_state != state)
rx_data_valid <= 1'b1;
else if(state == S_DATA && rx_data_ready)
rx_data_valid <= 1'b0;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
rx_data <= 8'd0;
else if(state == S_STOP && next_state != state)
rx_data <= rx_bits;//latch received data
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
begin
bit_cnt <= 3'd0;
end
else if(state == S_REC_BYTE)
if(cycle_cnt == CYCLE - 1)
bit_cnt <= bit_cnt + 3'd1;
else
bit_cnt <= bit_cnt;
else
bit_cnt <= 3'd0;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
cycle_cnt <= 16'd0;
else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
cycle_cnt <= 16'd0;
else
cycle_cnt <= cycle_cnt + 16'd1;
end
//receive serial data bit data
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
rx_bits <= 8'd0;
else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
rx_bits[bit_cnt] <= rx_pin;
else
rx_bits <= rx_bits;
end
endmodule

133
Semaine_4/UART_FIFO/IP/verilog/other_tx.v Normal file
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@@ -0,0 +1,133 @@
module other_uart_tx
#(
parameter CLK_FRE = 27, //clock frequency(Mhz)
parameter BAUD_RATE = 115200 //serial baud rate
)
(
input clk, //clock input
input rst_n, //asynchronous reset input, low active
input[7:0] tx_data, //data to send
input tx_data_valid, //data to be sent is valid
output reg tx_data_ready, //send ready
output tx_pin //serial data output
);
//calculates the clock cycle for baud rate
localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE;
//state machine code
localparam S_IDLE = 1;
localparam S_START = 2;//start bit
localparam S_SEND_BYTE = 3;//data bits
localparam S_STOP = 4;//stop bit
reg[2:0] state;
reg[2:0] next_state;
reg[15:0] cycle_cnt; //baud counter
reg[2:0] bit_cnt;//bit counter
reg[7:0] tx_data_latch; //latch data to send
reg tx_reg; //serial data output
assign tx_pin = tx_reg;
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
state <= S_IDLE;
else
state <= next_state;
end
always@(*)
begin
case(state)
S_IDLE:
if(tx_data_valid == 1'b1)
next_state <= S_START;
else
next_state <= S_IDLE;
S_START:
if(cycle_cnt == CYCLE - 1)
next_state <= S_SEND_BYTE;
else
next_state <= S_START;
S_SEND_BYTE:
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
next_state <= S_STOP;
else
next_state <= S_SEND_BYTE;
S_STOP:
if(cycle_cnt == CYCLE - 1)
next_state <= S_IDLE;
else
next_state <= S_STOP;
default:
next_state <= S_IDLE;
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
begin
tx_data_ready <= 1'b0;
end
else if(state == S_IDLE)
if(tx_data_valid == 1'b1)
tx_data_ready <= 1'b0;
else
tx_data_ready <= 1'b1;
else if(state == S_STOP && cycle_cnt == CYCLE - 1)
tx_data_ready <= 1'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
begin
tx_data_latch <= 8'd0;
end
else if(state == S_IDLE && tx_data_valid == 1'b1)
tx_data_latch <= tx_data;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
begin
bit_cnt <= 3'd0;
end
else if(state == S_SEND_BYTE)
if(cycle_cnt == CYCLE - 1)
bit_cnt <= bit_cnt + 3'd1;
else
bit_cnt <= bit_cnt;
else
bit_cnt <= 3'd0;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
cycle_cnt <= 16'd0;
else if((state == S_SEND_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
cycle_cnt <= 16'd0;
else
cycle_cnt <= cycle_cnt + 16'd1;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
tx_reg <= 1'b1;
else
case(state)
S_IDLE,S_STOP:
tx_reg <= 1'b1;
S_START:
tx_reg <= 1'b0;
S_SEND_BYTE:
tx_reg <= tx_data_latch[bit_cnt];
default:
tx_reg <= 1'b1;
endcase
end
endmodule

145
Semaine_4/UART_FIFO/IP/verilog/uart_rx.v Normal file
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@@ -0,0 +1,145 @@
module uart_rx #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200
)(
input clk, //clock input
input rst_p, //asynchronous reset input, high active
input rx_enable, //data receiver module ready
input rx_pin, //serial data input
output reg[7:0] rx_data, //received serial data
output reg rx_received //received serial data is valid
);
localparam CYCLE = CLK_FREQ / BAUD_RATE;
//state machine code
localparam S_IDLE = 1;
localparam S_START = 2; //start bit
localparam S_REC_BYTE = 3; //data bits
localparam S_STOP = 4; //stop bit
localparam S_DATA = 5;
reg[2:0] state;
reg[2:0] next_state;
reg rx_d0; //delay 1 clock for rx_pin
reg rx_d1; //delay 1 clock for rx_d0
wire rx_negedge; //negedge of rx_pin
reg[7:0] rx_bits; //temporary storage of received data
reg[15:0] cycle_cnt; //baud counter
reg[2:0] bit_cnt; //bit counter
assign rx_negedge = rx_d1 && ~rx_d0; // Front déscendant
always@(posedge clk or posedge rst_p) // Filtrage du signial
begin
if(rst_p == 1'b1)begin
rx_d0 <= 1'b0;
rx_d1 <= 1'b0;
end else begin
rx_d0 <= rx_pin;
rx_d1 <= rx_d0;
end
end
always@(posedge clk or posedge rst_p)begin // Compteur d'etat
if(rst_p == 1'b1)
state <= S_IDLE;
else
state <= next_state;
end
always@(*)begin
case(state)
S_IDLE:
if(rx_negedge) // Detection du start bit
next_state = S_START;
else
next_state = S_IDLE;
S_START:
if(cycle_cnt == CYCLE - 1) //one data cycle
next_state = S_REC_BYTE;
else
next_state = S_START;
S_REC_BYTE:
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data
next_state = S_STOP;
else
next_state = S_REC_BYTE;
S_STOP:
if(cycle_cnt == CYCLE/2 - 1) //half bit cycle,to avoid missing the next byte receiver
next_state = S_DATA;
else
next_state = S_STOP;
S_DATA:
if(rx_enable) //data receive complete
next_state = S_IDLE;
else
next_state = S_DATA;
default:
next_state = S_IDLE;
endcase
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
rx_received <= 1'b0;
else if(state == S_STOP && next_state != state)
rx_received <= 1'b1;
else if(state == S_DATA && rx_enable)
rx_received <= 1'b0;
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
rx_data <= 8'd0;
else if(state == S_STOP && next_state != state)
rx_data <= rx_bits;//latch received data
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
begin
bit_cnt <= 3'd0;
end
else if(state == S_REC_BYTE)
if(cycle_cnt == CYCLE - 1)
bit_cnt <= bit_cnt + 3'd1;
else
bit_cnt <= bit_cnt;
else
bit_cnt <= 3'd0;
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
cycle_cnt <= 16'd0;
else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
cycle_cnt <= 16'd0;
else
cycle_cnt <= cycle_cnt + 16'd1;
end
//receive serial data bit data
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
rx_bits <= 8'd0;
else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
rx_bits[bit_cnt] <= rx_pin;
else
rx_bits <= rx_bits;
end
endmodule

131
Semaine_4/UART_FIFO/IP/verilog/uart_tx.v Normal file
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@@ -0,0 +1,131 @@
module uart_tx #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200
)(
input wire clk,
input wire rst_p,
input wire[7:0] data,
input wire tx_enable,
output reg tx_ready,
output wire tx
);
localparam CYCLE = CLK_FREQ / BAUD_RATE;
localparam IDLE = 2'd0;
localparam START = 2'd1;
localparam DATA = 2'd2;
localparam STOP = 2'd3;
reg [1:0] state = IDLE;
reg [1:0] next_state;
reg [15:0] cycle_cnt; //baud counter
reg tx_reg;
reg [2:0] bit_cnt;
reg [7:0] tx_data_latch = 0;
assign tx = tx_reg;
always@(posedge clk or posedge rst_p)begin // Avance d'etat
if(rst_p == 1'b1)
state <= IDLE;
else
state <= next_state;
end
always@(*) begin
case(state)
IDLE:
if(tx_enable == 1'b1)
next_state = START;
else
next_state = IDLE;
START:
if(cycle_cnt == CYCLE - 1)
next_state = DATA;
else
next_state = START;
DATA:
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
next_state = STOP;
else
next_state = DATA;
STOP:
if(cycle_cnt == CYCLE - 1)
next_state = IDLE;
else
next_state = STOP;
default:
next_state = IDLE;
endcase
end
always@(posedge clk or posedge rst_p)begin // tx_ready block
if(rst_p == 1'b1)
tx_ready <= 1'b0; // Reset
else if(state == IDLE && tx_enable == 1'b1)
tx_ready <= 1'b0; // Pas prêt tant que les données sont valides
else if(state == IDLE)
tx_ready <= 1'b1;
else if(state == STOP && cycle_cnt == CYCLE - 1)
tx_ready <= 1'b1; // Prêt une fois le bit STOP envoyé
else
tx_ready <= tx_ready; // Reste inchangé dans d'autres cas
end
always@(posedge clk or posedge rst_p) begin // tx_data_latch block
if(rst_p == 1'b1) begin
tx_data_latch <= 8'd0;
end else if(state == IDLE && tx_enable == 1'b1) begin
tx_data_latch <= data; // Charger les données de data dans tx_data_latch
end
end
always@(posedge clk or posedge rst_p)begin // DATA bit_cnt block
if(rst_p == 1'b1)begin
bit_cnt <= 3'd0;
end else if(state == DATA)
if(cycle_cnt == CYCLE - 1)
bit_cnt <= bit_cnt + 3'd1;
else
bit_cnt <= bit_cnt;
else
bit_cnt <= 3'd0;
end
always@(posedge clk or posedge rst_p)begin // Cycle counter
if(rst_p == 1'b1)
cycle_cnt <= 16'd0;
else if((state == DATA && cycle_cnt == CYCLE - 1) || next_state != state)
cycle_cnt <= 16'd0;
else
cycle_cnt <= cycle_cnt + 16'd1;
end
always@(posedge clk or posedge rst_p)begin // tx state managment
if(rst_p == 1'b1)
tx_reg <= 1'b1;
else
case(state)
IDLE,STOP:
tx_reg <= 1'b1;
START:
tx_reg <= 1'b0;
DATA:
tx_reg <= tx_data_latch[bit_cnt]; // SENDING BYTE HERE
default:
tx_reg <= 1'b1;
endcase
end
endmodule

2
Semaine_4/UART_FIFO/scripts/gtkwave.bat
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@@ -1,3 +1,3 @@
@echo off @echo off
echo === Lancement de GTKWave === echo === Lancement de GTKWave ===
gtkwave runs/uart.vcd gtkwave runs/uart_tx_fifo.vcd

2
Semaine_4/UART_FIFO/scripts/simulate.bat
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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp set OUT=runs/sim.vvp
:: Top-level testbench module :: Top-level testbench module
set TOP=tb_uart set TOP=tb_uart_tx_fifo
:: Répertoires contenant des fichiers .v :: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog set DIRS=src/verilog tests/verilog IP/verilog

183
Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v
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@@ -1,145 +1,68 @@
module uart_rx #( module uart_rx_fifo #(
parameter CLK_FREQ = 27_000_000, parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200 parameter BAUD_RATE = 115200,
parameter FIFO_DEPTH = 8
)( )(
input clk, //clock input input clk,
input rst_p, //asynchronous reset input, high active input rd_en,
input rx_enable, //data receiver module ready output reg [7:0] rd_data,
input rx_pin, //serial data input input rx_pin,
output data_available
output reg[7:0] rx_data, //received serial data
output reg rx_received //received serial data is valid
); );
localparam CYCLE = CLK_FREQ / BAUD_RATE; // UART RX wires
wire [7:0] rx_data;
wire rx_received;
//state machine code // FIFO control
localparam S_IDLE = 1; reg wr_en;
localparam S_START = 2; //start bit wire fifo_empty;
localparam S_REC_BYTE = 3; //data bits wire fifo_full;
localparam S_STOP = 4; //stop bit wire [7:0] fifo_rd_data;
localparam S_DATA = 5;
reg[2:0] state; // UART Receiver instance
reg[2:0] next_state; uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) uart_rx_inst (
.clk(clk),
.rst_p(1'b0),
.rx_enable(1'b1),
.rx_pin(rx_pin),
.rx_data(rx_data),
.rx_received(rx_received)
);
reg rx_d0; //delay 1 clock for rx_pin // FIFO instance
reg rx_d1; //delay 1 clock for rx_d0 fifo #(
wire rx_negedge; //negedge of rx_pin .WIDTH(8),
reg[7:0] rx_bits; //temporary storage of received data .DEPTH(FIFO_DEPTH)
reg[15:0] cycle_cnt; //baud counter ) fifo_inst (
reg[2:0] bit_cnt; //bit counter .clk(clk),
.wr_en(wr_en),
.wr_data(rx_data),
.rd_en(rd_en),
.rd_data(fifo_rd_data),
.empty(fifo_empty),
.full(fifo_full)
);
assign rx_negedge = rx_d1 && ~rx_d0; // Front déscendant assign data_available = ~fifo_empty;
always@(posedge clk or posedge rst_p) // Filtrage du signial // Enregistrement explicite des données lues pour stabilité
begin always @(posedge clk) begin
if(rst_p == 1'b1)begin if (rd_en && !fifo_empty) begin
rx_d0 <= 1'b0; rd_data <= fifo_rd_data;
rx_d1 <= 1'b0; end
end
// Écriture dans la FIFO uniquement si donnée reçue ET FIFO pas pleine
always @(posedge clk) begin
if (rx_received && !fifo_full) begin
wr_en <= 1'b1;
end else begin end else begin
rx_d0 <= rx_pin; wr_en <= 1'b0;
rx_d1 <= rx_d0;
end end
end end
always@(posedge clk or posedge rst_p)begin // Compteur d'etat
if(rst_p == 1'b1)
state <= S_IDLE;
else
state <= next_state;
end
always@(*)begin
case(state)
S_IDLE:
if(rx_negedge) // Detection du start bit
next_state = S_START;
else
next_state = S_IDLE;
S_START:
if(cycle_cnt == CYCLE - 1) //one data cycle
next_state = S_REC_BYTE;
else
next_state = S_START;
S_REC_BYTE:
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data
next_state = S_STOP;
else
next_state = S_REC_BYTE;
S_STOP:
if(cycle_cnt == CYCLE/2 - 1) //half bit cycle,to avoid missing the next byte receiver
next_state = S_DATA;
else
next_state = S_STOP;
S_DATA:
if(rx_enable) //data receive complete
next_state = S_IDLE;
else
next_state = S_DATA;
default:
next_state = S_IDLE;
endcase
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
rx_received <= 1'b0;
else if(state == S_STOP && next_state != state)
rx_received <= 1'b1;
else if(state == S_DATA && rx_enable)
rx_received <= 1'b0;
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
rx_data <= 8'd0;
else if(state == S_STOP && next_state != state)
rx_data <= rx_bits;//latch received data
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
begin
bit_cnt <= 3'd0;
end
else if(state == S_REC_BYTE)
if(cycle_cnt == CYCLE - 1)
bit_cnt <= bit_cnt + 3'd1;
else
bit_cnt <= bit_cnt;
else
bit_cnt <= 3'd0;
end
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
cycle_cnt <= 16'd0;
else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
cycle_cnt <= 16'd0;
else
cycle_cnt <= cycle_cnt + 16'd1;
end
//receive serial data bit data
always@(posedge clk or posedge rst_p)
begin
if(rst_p == 1'b1)
rx_bits <= 8'd0;
else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
rx_bits[bit_cnt] <= rx_pin;
else
rx_bits <= rx_bits;
end
endmodule endmodule

187
Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v
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@@ -1,131 +1,86 @@
module uart_tx #( module uart_tx_fifo #(
parameter CLK_FREQ = 27_000_000, parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200 parameter BAUD_RATE = 115200,
parameter FIFO_DEPTH = 8
)( )(
input wire clk, input clk,
input wire rst_p, input wr_en,
input wire[7:0] data, input [7:0] wr_data,
input wire tx_enable, output tx_pin,
output fifo_full
output reg tx_ready,
output wire tx
); );
localparam CYCLE = CLK_FREQ / BAUD_RATE; // FIFO wires
wire [7:0] fifo_rd_data;
wire fifo_empty;
reg fifo_rd_en;
localparam IDLE = 2'd0; // UART wires
localparam START = 2'd1; wire tx_ready;
localparam DATA = 2'd2; reg uart_tx_enable;
localparam STOP = 2'd3; reg [7:0] uart_tx_data;
reg [1:0] state = IDLE; // FSM
reg [1:0] next_state; typedef enum logic [1:0] {
reg [15:0] cycle_cnt; //baud counter IDLE,
reg tx_reg; WAIT_READY,
reg [2:0] bit_cnt; SEND
reg [7:0] tx_data_latch = 0; } state_t;
state_t state = IDLE;
assign tx = tx_reg; // FIFO instantiation
fifo #(
.WIDTH(8),
.DEPTH(FIFO_DEPTH)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),
.wr_data(wr_data),
.rd_en(fifo_rd_en),
.rd_data(fifo_rd_data),
.empty(fifo_empty),
.full(fifo_full)
);
always@(posedge clk or posedge rst_p)begin // Avance d'etat // UART TX instantiation
if(rst_p == 1'b1) uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) uart_tx_inst (
.clk(clk),
.rst_p(1'b0),
.data(uart_tx_data),
.tx_enable(uart_tx_enable),
.tx_ready(tx_ready),
.tx(tx_pin)
);
always_ff @(posedge clk) begin
// Valeurs par défaut
fifo_rd_en <= 0;
uart_tx_enable <= 0;
case (state)
IDLE: begin
if (!fifo_empty) begin
state <= WAIT_READY;
end
end
WAIT_READY: begin
if (tx_ready) begin
fifo_rd_en <= 1;
state <= SEND;
end
end
SEND: begin
uart_tx_data <= fifo_rd_data;
uart_tx_enable <= 1;
state <= IDLE; state <= IDLE;
else
state <= next_state;
end end
always@(*) begin
case(state)
IDLE:
if(tx_enable == 1'b1)
next_state = START;
else
next_state = IDLE;
START:
if(cycle_cnt == CYCLE - 1)
next_state = DATA;
else
next_state = START;
DATA:
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
next_state = STOP;
else
next_state = DATA;
STOP:
if(cycle_cnt == CYCLE - 1)
next_state = IDLE;
else
next_state = STOP;
default:
next_state = IDLE;
endcase endcase
end end
always@(posedge clk or posedge rst_p)begin // tx_ready block
if(rst_p == 1'b1)
tx_ready <= 1'b0; // Reset
else if(state == IDLE && tx_enable == 1'b1)
tx_ready <= 1'b0; // Pas prêt tant que les données sont valides
else if(state == IDLE)
tx_ready <= 1'b1;
else if(state == STOP && cycle_cnt == CYCLE - 1)
tx_ready <= 1'b1; // Prêt une fois le bit STOP envoyé
else
tx_ready <= tx_ready; // Reste inchangé dans d'autres cas
end
always@(posedge clk or posedge rst_p) begin // tx_data_latch block
if(rst_p == 1'b1) begin
tx_data_latch <= 8'd0;
end else if(state == IDLE && tx_enable == 1'b1) begin
tx_data_latch <= data; // Charger les données de `data` dans `tx_data_latch`
end
end
always@(posedge clk or posedge rst_p)begin // DATA bit_cnt block
if(rst_p == 1'b1)begin
bit_cnt <= 3'd0;
end else if(state == DATA)
if(cycle_cnt == CYCLE - 1)
bit_cnt <= bit_cnt + 3'd1;
else
bit_cnt <= bit_cnt;
else
bit_cnt <= 3'd0;
end
always@(posedge clk or posedge rst_p)begin // Cycle counter
if(rst_p == 1'b1)
cycle_cnt <= 16'd0;
else if((state == DATA && cycle_cnt == CYCLE - 1) || next_state != state)
cycle_cnt <= 16'd0;
else
cycle_cnt <= cycle_cnt + 16'd1;
end
always@(posedge clk or posedge rst_p)begin // tx state managment
if(rst_p == 1'b1)
tx_reg <= 1'b1;
else
case(state)
IDLE,STOP:
tx_reg <= 1'b1;
START:
tx_reg <= 1'b0;
DATA:
tx_reg <= tx_data_latch[bit_cnt]; // SENDING BYTE HERE
default:
tx_reg <= 1'b1;
endcase
end
endmodule endmodule

60
Semaine_4/UART_FIFO/tests/verilog/tb_uart_rx_fifo.v
View File

@@ -1,6 +1,6 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module tb_uart_rx; module tb_uart_rx_fifo;
reg clk = 0; reg clk = 0;
reg rx; reg rx;
@@ -10,8 +10,8 @@ module tb_uart_rx;
reg tx_data_valid; reg tx_data_valid;
reg tx_data_ready; reg tx_data_ready;
reg rx_received; reg rd_en;
wire rx_enable = 1'b1; // Enable the receiver wire data_available;
localparam CLK_FREQ = 27_000_000; localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200; localparam BAUD_RATE = 115_200;
@@ -27,23 +27,24 @@ module tb_uart_rx;
.rst_n(1'b1) .rst_n(1'b1)
); );
uart_rx #( uart_rx_fifo #(
.CLK_FREQ(CLK_FREQ), .CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE) .BAUD_RATE(BAUD_RATE),
) rx_instance ( .FIFO_DEPTH(8)
) rx_fifo_instance (
.clk(clk), .clk(clk),
.rx_pin(rx), .rx_pin(rx),
.rx_data(data_out), .rd_en(rd_en),
.rx_received(rx_received), .rd_data(data_out),
.rx_enable(rx_enable) .data_available(data_available)
); );
always #(CLK_PERIOD_NS/2) clk = ~clk; always #(CLK_PERIOD_NS/2) clk = ~clk;
initial begin initial begin
$dumpfile("runs/uart_rx.vcd"); $dumpfile("runs/uart_rx_fifo.vcd");
$dumpvars(0, tb_uart_rx); $dumpvars(0, tb_uart_rx_fifo);
$display("======== Start UART RX test ========="); $display("======== Start UART RX FIFO test =========");
#100; #100;
data_in = 8'd123; // Data to send data_in = 8'd123; // Data to send
@@ -56,12 +57,41 @@ module tb_uart_rx;
tx_data_valid = 1'b0; // Clear the valid signal tx_data_valid = 1'b0; // Clear the valid signal
wait(rx_received); // Wait for the receiver to receive the data data_in = 8'd234; // Data to send
wait(tx_data_ready); // Wait for the transmitter to be ready
#1; // Small delay to ensure the data is latched
$display("Data sent: %d", data_in); tx_data_valid = 1'b1; // Indicate that the data is valid
wait(tx_data_ready == 0);
tx_data_valid = 1'b0; // Clear the valid signal
data_in = 8'd101; // Data to send
wait(tx_data_ready); // Wait for the transmitter to be ready
#1; // Small delay to ensure the data is latched
tx_data_valid = 1'b1; // Indicate that the data is valid
wait(tx_data_ready == 0);
tx_data_valid = 1'b0; // Clear the valid signal
wait(data_available); // Wait for the receiver to receive the data
rd_en = 1'b1; // Enable read from FIFO
#37; // Small delay to ensure the data is read
$display("Data received: %d", data_out); // Display the received data $display("Data received: %d", data_out); // Display the received data
rd_en = 1'b0; // Disable read from FIFO
#37; // Small delay to ensure the data is read
$display("======== END UART RX test ========="); rd_en = 1'b1; // Enable read from FIFO
#37; // Small delay to ensure the data is read
$display("Data received: %d", data_out); // Display the received data
rd_en = 1'b0; // Disable read from FIFO
#37; // Small delay to ensure the data is read
$display("======== END UART RX FIFO test =========");
$finish; $finish;
end end
endmodule endmodule

70
Semaine_4/UART_FIFO/tests/verilog/tb_uart_tx_fifo.v
View File

@@ -1,16 +1,17 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module tb_uart_tx; module tb_uart_tx_fifo;
reg clk = 0; reg clk = 0;
reg tx_enable = 0;
reg [7:0] data_in = 8'h00; reg [7:0] data_in = 8'h00;
reg [7:0] data_out; reg [7:0] data_out;
wire tx; wire tx;
reg tx_ready;
wire rx_recieved; wire rx_recieved;
wire fifo_full;
reg wr_en = 0;
always #18.5 clk = ~clk; always #18.5 clk = ~clk;
other_uart_rx rx_instance( other_uart_rx rx_instance(
@@ -22,55 +23,44 @@ module tb_uart_tx;
.rx_data_ready(1'b1) .rx_data_ready(1'b1)
); );
uart_tx #( uart_tx_fifo #(
.CLK_FREQ(27_000_000), .CLK_FREQ(27_000_000),
.BAUD_RATE(115_200) .BAUD_RATE(115_200),
)tx_instance ( .FIFO_DEPTH(8)
)tx_fifo_instance (
.clk(clk), .clk(clk),
.tx_enable(tx_enable), .wr_en(wr_en),
.tx_ready(tx_ready), .wr_data(data_in),
.data(data_in), .tx_pin(tx),
.tx(tx), .fifo_full(fifo_full)
.rst_p(1'b0)
); );
initial begin initial begin
$dumpfile("runs/uart_tx.vcd"); $dumpfile("runs/uart_tx_fifo.vcd");
$dumpvars(0, tb_uart_tx); $dumpvars(0, tb_uart_tx_fifo);
$display("======== Start UART TX test ========="); $display("======== Start UART TX FIFO test =========");
#100; #50;
data_in <= 8'd234; // 234 data_in <= 8'd234;
tx_enable <= 1; wr_en <= 1'b1; // Activer l'écriture dans la FIFO
wait(tx_ready == 1'b0); #37;
tx_enable <= 0; wr_en <= 1'b0; // Désactiver l'écriture dans la FIFO
// Attendre data_in <= 8'd123;
wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif wr_en <= 1'b1; // Activer l'écriture dans la FIFO
#37;
wr_en <= 1'b0; // Désactiver l'écriture dans la FIFO
$display("Data received: %d", data_out); // Afficher la valeur recu data_in <= 8'd45;
$display("Data expected: %d", data_in); // Afficher la valeur envoyee wr_en <= 1'b1; // Activer l'écriture dans la FIFO
#37;
wr_en <= 1'b0; // Désactiver l'écriture dans la FIFO
#1000; $display("======== END UART TX FIFO test =========");
wait(tx_ready == 1'b1); // Attendre que le signal de reception soit actif #1000000;
data_in <= 8'd202; // 202
tx_enable <= 1;
wait(tx_ready == 1'b0);
tx_enable <= 0;
// Attendre
wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
$display("======== END UART TX test =========");
#1000;
$stop; $stop;
end end