verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

uart modules work

Browse Source
This commit is contained in:
Gamenight77
2025-05-05 09:58:19 +02:00
parent fc48941459
commit 87732dcf87
3 changed files with 86 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Semaine_4/UART/scripts/gtkwave.bat
View File

@@ -1,3 +1,3 @@
@echo off
echo === Lancement de GTKWave ===
gtkwave runs/uart_rx.vcd
gtkwave runs/uart.vcd

2
Semaine_4/UART/scripts/simulate.bat
View File

@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=tb_uart_rx
set TOP=tb_uart
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog