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forked from tanchou/Verilog

uart modules work

This commit is contained in:
Gamenight77
2025-05-05 09:58:19 +02:00
parent fc48941459
commit 87732dcf87
3 changed files with 86 additions and 2 deletions

View File

@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=tb_uart_rx
set TOP=tb_uart
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog