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Add WAIT state to FSM and implement delay mechanism in UART module

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This commit is contained in:
Gamenight77
2025-05-07 18:07:45 +02:00
parent 6bb42700f8
commit 93e0e96798
1 changed files with 13 additions and 2 deletions
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13
Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v
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@@ -37,9 +37,11 @@ module top_uart_ultrason (
); );
// === FSM === // === FSM ===
localparam IDLE = 0, SEND_LOW = 2, SEND_HIGH = 3; localparam IDLE = 0, WAIT = 1 ,SEND_LOW = 2, SEND_HIGH = 3;
reg [1:0] state = IDLE; reg [1:0] state = IDLE;
reg [8:0] delay_counter = 0;
always @(posedge clk) begin always @(posedge clk) begin
// Activer en continu tant que FIFO pas pleine // Activer en continu tant que FIFO pas pleine
start <= 1; start <= 1;
@@ -61,7 +63,16 @@ module top_uart_ultrason (
SEND_HIGH: begin SEND_HIGH: begin
wr_data <= distance[15:8]; // Octet MSB wr_data <= distance[15:8]; // Octet MSB
state <= WAIT;
end
WAIT: begin // Code non testé
if (delay_counter < 1000000) begin
delay_counter <= delay_counter + 1;
end else begin
state <= IDLE; state <= IDLE;
delay_counter <= 0;
end
end end
endcase endcase