Add WAIT state to FSM and implement delay mechanism in UART module

Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v

@@ -37,9 +37,11 @@ module top_uart_ultrason (
     );
 
     // === FSM ===
-    localparam IDLE = 0, SEND_LOW = 2, SEND_HIGH = 3;
+    localparam IDLE = 0, WAIT = 1 ,SEND_LOW = 2, SEND_HIGH = 3;
     reg [1:0] state = IDLE;
 
+    reg [8:0] delay_counter = 0;
+
     always @(posedge clk) begin
         // Activer en continu tant que FIFO pas pleine
         start <= 1;
@@ -61,7 +63,16 @@ module top_uart_ultrason (
 
             SEND_HIGH: begin
                 wr_data <= distance[15:8]; // Octet MSB
+                state <= WAIT;
+            end
+
+            WAIT: begin // Code non testé
+                if (delay_counter < 1000000) begin
+                    delay_counter <= delay_counter + 1;
+                end else begin
                     state <= IDLE;
+                    delay_counter <= 0;
+                end
             end
 
         endcase