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forked from tanchou/Verilog

Add UART communication modules and testbenches

- Implemented rx_fifo module for receiving data with FIFO management.
- Created tb_top_uart_rx_tx testbench for testing UART transmission and reception.
- Developed tb_uart_rx testbench for validating UART receiver functionality.
- Added tb_uart_tx testbench for testing UART transmitter behavior.
- Designed top_led_uart module to interface UART with LED outputs.
- Integrated top_uart_ultrasonic module for ultrasonic sensor data transmission via UART.
- Implemented tx_fifo module for transmitting data with FIFO management.
- Developed uart_rx module for receiving serial data with state machine control.
- Created uart_top module to connect RX and TX functionalities with FIFO buffers.
- Implemented uart_tx module for transmitting serial data with state machine control.
This commit is contained in:
Gamenight77
2025-04-28 17:13:39 +02:00
parent 596d47d356
commit 96c234de6d
11 changed files with 846 additions and 0 deletions

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