forked from tanchou/Verilog
96c234de6d
- Implemented rx_fifo module for receiving data with FIFO management. - Created tb_top_uart_rx_tx testbench for testing UART transmission and reception. - Developed tb_uart_rx testbench for validating UART receiver functionality. - Added tb_uart_tx testbench for testing UART transmitter behavior. - Designed top_led_uart module to interface UART with LED outputs. - Integrated top_uart_ultrasonic module for ultrasonic sensor data transmission via UART. - Implemented tx_fifo module for transmitting data with FIFO management. - Developed uart_rx module for receiving serial data with state machine control. - Created uart_top module to connect RX and TX functionalities with FIFO buffers. - Implemented uart_tx module for transmitting serial data with state machine control.
Verilog
Semaine 1
Semaine 2
Cheat sheet
Commands
Compile code iverilog -o Nom_de_sortie.vvp .\source1.v .\tb_1.v
Upload on fpga
rem https://github.com/YosysHQ/apicula yosys -p "read_verilog blink_led.v; synth_gowin -json blink_led_c.json"
set DEVICE=GW2AR-LV18QN88C8/I7 set BOARD=tangnano20k
nextpnr-himbaechel --json blink_led_c.json --write pnr_blink_led.json --device %DEVICE% --vopt cst=blink_led.cst --vopt family=GW2A-18C
gowin_pack -d %DEVICE% -o blink_led_c.fs pnr_blink_led.json
openfpgaloader -b %BOARD% blink_led_c.fs