forked from tanchou/Verilog
Add UART communication modules and testbenches
- Implemented rx_fifo module for receiving data with FIFO management. - Created tb_top_uart_rx_tx testbench for testing UART transmission and reception. - Developed tb_uart_rx testbench for validating UART receiver functionality. - Added tb_uart_tx testbench for testing UART transmitter behavior. - Designed top_led_uart module to interface UART with LED outputs. - Integrated top_uart_ultrasonic module for ultrasonic sensor data transmission via UART. - Implemented tx_fifo module for transmitting data with FIFO management. - Developed uart_rx module for receiving serial data with state machine control. - Created uart_top module to connect RX and TX functionalities with FIFO buffers. - Implemented uart_tx module for transmitting serial data with state machine control.
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69
Semaine_3/UARTV2/tb_top_uart_rx_tx.v
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69
Semaine_3/UARTV2/tb_top_uart_rx_tx.v
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`timescale 1ns / 1ps
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module tb_top_uart_rx_tx;
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parameter CLK_FREQ = 27_000_000;
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parameter BAUD_RATE = 115200;
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// Signaux
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reg clk = 0;
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reg start = 0;
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reg [7:0] data_in = 0;
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wire [7:0] data_out;
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wire valid;
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wire tx;
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wire rx; // On connecte tx directement à rx pour le test
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// Instance du module à tester
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top_uart_rx_tx #(
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.CLK_FREQ(CLK_FREQ),
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.BAUD_RATE(BAUD_RATE)
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) uut (
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.clk(clk),
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.start(start),
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.data_in(data_in),
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.rx(rx),
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.data_out(data_out),
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.valid(valid),
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.tx(tx)
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);
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// Boucle le tx sur rx
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assign rx = tx;
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// Clock à 50 MHz (20 ns période)
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always #10 clk = ~clk;
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// Simulation principale
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initial begin
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$display("Début de la simulation");
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$dumpfile("uart_loopback.vcd"); // Pour GTKWave
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$dumpvars(0, tb_top_uart_rx_tx);
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// Attendre un peu
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#(20 * 10);
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// Envoi d'une valeur
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data_in = 8'hA5; // Exemple de data
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start = 1;
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#20;
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start = 0;
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// Attendre la réception (valeur valid = 1)
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wait(valid == 1);
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// Affichage des résultats
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$display("Data envoyee : 0x%h", data_in);
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$display("Data recue : 0x%h", data_out);
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if (data_out == data_in)
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$display("Test reussi !");
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else
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$display("Test echoue...");
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// Fin de simulation
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#(20 * 10);
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$finish;
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end
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endmodule
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