MAJ FIFO -> turn wire rd_data into register

2025-05-09 10:27:13 +02:00
parent cd14d82add
commit 99e259f672
2 changed files with 10 additions and 12 deletions
--- a/Semaine_4/UART/src/verilog/top_uart_loopback1.v
+++ b/Semaine_4/UART/src/verilog/top_uart_loopback1.v
@@ -120,13 +120,11 @@ localparam DATA_BYTE = 8'h31; // ASCII '1'
            tx_enable <= 1'b0;
            leds[5:0] <= rx_data[5:0];
            
-            if (tx_ready && delay_counter == 0) begin
+            if (tx_ready && rx_received) begin
                // Start new transmission
                tx_enable <= 1'b1;
                data_const <= DATA_BYTE;
                tx_data <= rx_data; 
-
-                 // Display received data on LEDs
            
                delay_counter <= DELAY_CYCLES;
            end