Refactor DHT11 model: update clock comment for clarity and adjust state machine comment formatting

2025-05-22 08:58:27 +02:00
parent 434381e9b6
commit a541e033d7
1 changed files with 2 additions and 2 deletions
--- a/Semaine_6/DHT11/src/verilog/dht11_model.v
+++ b/Semaine_6/DHT11/src/verilog/dht11_model.v
@@ -1,6 +1,6 @@
 module dht11_model (
    inout  wire data,          // Ligne de données bidirectionnelle
-    input  wire clk,           // Horloge système (27 MHz)
+    input  wire clk,           // (27 MHz)
    input  wire rst_n          // Reset actif bas
 );