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loopback fonctionne avec le rxuartlite

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Gamenight77
2025-05-09 09:15:28 +02:00
parent 93e0e96798
commit a792f85adf
3 changed files with 16 additions and 4 deletions
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4
Semaine_4/UART/IP/verilog/rxuartlite.v
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@@ -52,7 +52,7 @@ module rxuartlite #(
`ifdef FORMAL
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof
`else
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868, // 115200 Baud at 100MHz
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 234, // 115200 Baud at 100MHz
`endif
localparam TB = TIMER_BITS,
//
@@ -75,7 +75,7 @@ module rxuartlite #(
// {{{
input wire i_clk, i_reset,
input wire i_uart_rx,
output reg o_wr,
output reg o_wr,
output reg [7:0] o_data
// }}}
);