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loopback fonctionne avec le rxuartlite

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Gamenight77
2025-05-09 09:15:28 +02:00
parent 93e0e96798
commit a792f85adf
3 changed files with 16 additions and 4 deletions
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Semaine_4/UART/scripts/build.bat
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@@ -19,7 +19,7 @@ if not exist runs (
)
echo === Étape 1 : Synthèse avec Yosys ===
yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/other_rx.v IP/verilog/rxuartlite.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
yosys -p "read_verilog -sv src/verilog/%TOP%1.v IP/verilog/other_rx.v IP/verilog/rxuartlite.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
if errorlevel 1 goto error
echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===