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forked from tanchou/Verilog

Tb for fifo working fine

This commit is contained in:
Gamenight77
2025-05-06 09:14:59 +02:00
parent 1d39c68b5c
commit aaebf22d48
4 changed files with 88 additions and 5 deletions

View File

@@ -1,3 +1,3 @@
@echo off
echo === Lancement de GTKWave ===
gtkwave runs/uart.vcd
gtkwave runs/fifo.vcd

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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=tb_uart
set TOP=tb_fifo
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog