forked from tanchou/Verilog
Tb for fifo working fine
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@@ -1,4 +1,4 @@
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module uart_tx #(
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module fifo #(
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parameter DETPH = 16,
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parameter WIDTH = 8
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)(
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@@ -9,7 +9,7 @@
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output wire[WIDTH-1:0] rd_data,
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output wire full,
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output wire empty,
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output wire empty
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);
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reg [WIDTH-1:0] fifo[0:DETPH-1];
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@@ -21,6 +21,12 @@
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assign empty = (count == 0);
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assign rd_data = fifo[rd_ptr];
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initial begin
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wr_ptr = 0;
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rd_ptr = 0;
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count = 0;
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end
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always @(posedge clk) begin
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if (wr_en && !full) begin
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fifo[wr_ptr] <= wr_data;
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