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forked from tanchou/Verilog

Tb for fifo working fine

This commit is contained in:
Gamenight77
2025-05-06 09:14:59 +02:00
parent 1d39c68b5c
commit aaebf22d48
4 changed files with 88 additions and 5 deletions

View File

@@ -1,4 +1,4 @@
module uart_tx #(
module fifo #(
parameter DETPH = 16,
parameter WIDTH = 8
)(
@@ -9,7 +9,7 @@
output wire[WIDTH-1:0] rd_data,
output wire full,
output wire empty,
output wire empty
);
reg [WIDTH-1:0] fifo[0:DETPH-1];
@@ -21,6 +21,12 @@
assign empty = (count == 0);
assign rd_data = fifo[rd_ptr];
initial begin
wr_ptr = 0;
rd_ptr = 0;
count = 0;
end
always @(posedge clk) begin
if (wr_en && !full) begin
fifo[wr_ptr] <= wr_data;