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Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality

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This commit is contained in:
Gamenight77
2025-05-07 09:46:43 +02:00
parent 86d4f5ddd2
commit abef18227c
8 changed files with 75 additions and 62 deletions
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2
Semaine_4/UART/scripts/build.bat
View File

@@ -19,7 +19,7 @@ if not exist runs (
)
echo === Étape 1 : Synthèse avec Yosys ===
yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/other_rx.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
if errorlevel 1 goto error
echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===

47
Semaine_4/UART/src/verilog/top_uart_loopback.v
View File

@@ -17,23 +17,23 @@ module top_uart_loopback (
end
// === UART RX ===
uart_rx uart_rx_inst (
other_uart_rx uart_rx_inst (
.clk(clk),
.rst_p(1'b0),
.rst_n(1'b1),
.rx_pin(rx),
.rx_received(rx_received),
.rx_enable(1'b1),
.rx_data_valid(rx_received),
.rx_data_ready(1'b1),
.rx_data(rx_data)
);
// === UART TX ===
uart_tx uart_tx_inst (
other_uart_tx uart_tx_inst (
.clk(clk),
.rst_p(1'b0),
.data(tx_data),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.tx(tx)
.rst_n(1'b1),
.tx_data(tx_data),
.tx_data_valid(tx_enable),
.tx_data_ready(tx_ready),
.tx_pin(tx)
);
// === FSM avec délai ===
@@ -53,34 +53,33 @@ module top_uart_loopback (
if (rx_received && tx_ready) begin
tx_data <= rx_data;
state <= WAIT;
leds[0] <= 0;
leds[1] <= 1;
leds[0] <= 0;
leds[1] <= 1;
end
end
WAIT: begin
delay_counter <= delay_counter + 1;
if (delay_counter == 8'd400 && tx_ready) begin
tx_enable <= 1;
if (tx_ready) begin
tx_enable <= 1;
state <= SEND;
end else begin
tx_enable <= 0;
tx_enable <= 0;
end
leds[0] <= 1;
leds[1] <= 0;
end
SEND: begin
tx_enable <= 0;
state <= IDLE;
if (!tx_ready) begin // Attendre que la transmission commence
tx_enable <= 0;
end else if (tx_ready && tx_enable == 0) begin
state <= IDLE; // Transmission terminée, retour à l’attente
end
leds[0] <= 0;
leds[1] <= 0; // Envoi terminé
leds[1] <= 0;
end
endcase
end
endmodule