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forked from tanchou/Verilog

Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality

This commit is contained in:
Gamenight77
2025-05-07 09:46:43 +02:00
parent 86d4f5ddd2
commit abef18227c
8 changed files with 75 additions and 62 deletions