Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality

Semaine_4/UART_FIFO/scripts/build.bat

@@ -7,7 +7,7 @@ cd /d %~dp0\..
 rem === Config de base ===
 set DEVICE=GW2AR-LV18QN88C8/I7
 set BOARD=tangnano20k
-set TOP=top_uart_loopback
+set TOP=top_uart_loopback_fifo
 set CST_FILE=%TOP%.cst
 set JSON_FILE=runs/%TOP%.json
 set PNR_JSON=runs/pnr_%TOP%.json
@@ -19,7 +19,7 @@ if not exist runs (
 )
 
 echo === Étape 1 : Synthèse avec Yosys ===
-yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
+yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx_fifo.v src/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/uart_rx.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
 if errorlevel 1 goto error
 
 echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===

Semaine_4/UART_FIFO/scripts/gtkwave.bat

@@ -1,3 +1,3 @@
 @echo off
 echo === Lancement de GTKWave ===
-gtkwave runs/uart_tx_fifo.vcd
+gtkwave runs/uart_rx_fifo.vcd

Semaine_4/UART_FIFO/scripts/simulate.bat

@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
 set OUT=runs/sim.vvp
 
 :: Top-level testbench module
-set TOP=tb_uart_tx_fifo
+set TOP=tb_uart_rx_fifo
 
 :: Répertoires contenant des fichiers .v
 set DIRS=src/verilog tests/verilog IP/verilog