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Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality

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This commit is contained in:
Gamenight77
2025-05-07 09:46:43 +02:00
parent 86d4f5ddd2
commit abef18227c
8 changed files with 75 additions and 62 deletions
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4
Semaine_4/UART_FIFO/scripts/build.bat
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@@ -7,7 +7,7 @@ cd /d %~dp0\..
rem === Config de base ===
set DEVICE=GW2AR-LV18QN88C8/I7
set BOARD=tangnano20k
set TOP=top_uart_loopback
set TOP=top_uart_loopback_fifo
set CST_FILE=%TOP%.cst
set JSON_FILE=runs/%TOP%.json
set PNR_JSON=runs/pnr_%TOP%.json
@@ -19,7 +19,7 @@ if not exist runs (
)
echo === Étape 1 : Synthèse avec Yosys ===
yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx_fifo.v src/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/uart_rx.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
if errorlevel 1 goto error
echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===