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Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality

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This commit is contained in:
Gamenight77
2025-05-07 09:46:43 +02:00
parent 86d4f5ddd2
commit abef18227c
8 changed files with 75 additions and 62 deletions
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Semaine_4/UART_FIFO/scripts/simulate.bat
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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=tb_uart_tx_fifo
set TOP=tb_uart_rx_fifo
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog