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Gros patch sur la fifo et rx fifo pour gagner des tick d'horloge, uart comand fonctionne toujours pas

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This commit is contained in:
Gamenight77
2025-05-13 10:21:28 +02:00
parent cca81f4db5
commit b7d184d02f
13 changed files with 78 additions and 35 deletions
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2
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v
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@@ -34,8 +34,8 @@
end
if (rd_en && !empty) begin // OUT
rd_ptr <= (rd_ptr + 1) % SIZE;
rd_data <= fifo[rd_ptr];
rd_ptr <= (rd_ptr + 1) % SIZE;
count <= count - 1;
end
end

12
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_rx_fifo.v
View File

@@ -5,7 +5,7 @@ module uart_rx_fifo #(
)(
input clk,
input rd_en,
output reg [7:0] rd_data,
output wire [7:0] rd_data,
input rx_pin,
output data_available
);
@@ -18,7 +18,6 @@ module uart_rx_fifo #(
reg wr_en;
wire fifo_empty;
wire fifo_full;
wire [7:0] fifo_rd_data;
// UART Receiver instance
rxuartlite uart_rx_inst (
@@ -38,20 +37,13 @@ module uart_rx_fifo #(
.wr_en(wr_en),
.wr_data(rx_data),
.rd_en(rd_en),
.rd_data(fifo_rd_data),
.rd_data(rd_data),
.empty(fifo_empty),
.full(fifo_full)
);
assign data_available = ~fifo_empty;
// Enregistrement explicite des données lues pour stabilité
always @(posedge clk) begin
if (rd_en && !fifo_empty) begin
rd_data <= fifo_rd_data;
end
end
// Écriture dans la FIFO uniquement si donnée reçue ET FIFO pas pleine
always @(posedge clk) begin
if (rx_received && !fifo_full) begin

2
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_fpga.v
View File

@@ -54,7 +54,7 @@ module ultrasonic_fpga #(
case (state)
IDLE: begin
done <= 1;
done <= 0;
sig_out <= 0;
sig_dir <= 0;
distance <= 0;