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Gros patch sur la fifo et rx fifo pour gagner des tick d'horloge, uart comand fonctionne toujours pas

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This commit is contained in:
Gamenight77
2025-05-13 10:21:28 +02:00
parent cca81f4db5
commit b7d184d02f
13 changed files with 78 additions and 35 deletions
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16
Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
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@@ -52,7 +52,7 @@ module top_uart_ultrason_command (
);
// === FSM ===
localparam IDLE = 0, READ = 1;
localparam IDLE = 0, READ = 1, DECODE = 2;
localparam STOP = 3, ONE = 1, CONTINUOUS = 2;
reg [1:0] rx_state = IDLE;
@@ -84,6 +84,11 @@ module top_uart_ultrason_command (
READ: begin
leds [5] <= 1;
rd_en <= 1'b1;
rx_state <= DECODE;
end
DECODE: begin
case (rd_data)
8'h01: begin // Start mesure one mesure
start <= 1;
@@ -103,7 +108,7 @@ module top_uart_ultrason_command (
rx_state <= IDLE;
end
default: begin
default: begin
mesure <= STOP;
rx_state <= IDLE;
end
@@ -116,7 +121,9 @@ module top_uart_ultrason_command (
// Mesure block
always @(posedge clk) begin
leds <= mesure[1:0];
case (tx_state)
MESURE: begin
case (mesure)
STOP: begin // Stop mesure
@@ -128,9 +135,10 @@ module top_uart_ultrason_command (
if (done) begin
tx_state <= SEND_LOW;
wr_en <= 1;
mesure <= STOP;
end else begin
tx_state <= MESURE;
mesure <= STOP;
mesure <= ONE;
end
end
@@ -152,7 +160,7 @@ module top_uart_ultrason_command (
SEND_LOW: begin
wr_en <= 1;
wr_data <= distance[7:0]; // Octet LSB
tx_state <= SEND_HIGH;
tx_state <= WAIT;
end
SEND_HIGH: begin