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Gros patch sur la fifo et rx fifo pour gagner des tick d'horloge, uart comand fonctionne toujours pas

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Gamenight77
2025-05-13 10:21:28 +02:00
parent cca81f4db5
commit b7d184d02f
13 changed files with 78 additions and 35 deletions
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8
Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/.gitignore generated vendored Normal file
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# Default ignored files
/shelf/
/workspace.xml
# Editor-based HTTP Client requests
/httpRequests/
# Datasource local storage ignored files
/dataSources/
/dataSources.local.xml

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Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/Python.iml generated Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<module type="PYTHON_MODULE" version="4">
<component name="NewModuleRootManager">
<content url="file://$MODULE_DIR$" />
<orderEntry type="jdk" jdkName="Python 3.12" jdkType="Python SDK" />
<orderEntry type="sourceFolder" forTests="false" />
</component>
<component name="PyDocumentationSettings">
<option name="format" value="PLAIN" />
<option name="myDocStringFormat" value="Plain" />
</component>
</module>

6
Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/inspectionProfiles/profiles_settings.xml generated Normal file
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<component name="InspectionProjectProfileManager">
<settings>
<option name="USE_PROJECT_PROFILE" value="false" />
<version value="1.0" />
</settings>
</component>

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Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/misc.xml generated Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="ProjectRootManager" version="2" project-jdk-name="Python 3.12" project-jdk-type="Python SDK" />
</project>

8
Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/modules.xml generated Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="ProjectModuleManager">
<modules>
<module fileurl="file://$PROJECT_DIR$/.idea/Python.iml" filepath="$PROJECT_DIR$/.idea/Python.iml" />
</modules>
</component>
</project>

6
Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/vcs.xml generated Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="VcsDirectoryMappings">
<mapping directory="$PROJECT_DIR$/../../../.." vcs="Git" />
</component>
</project>

23
Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_ultrason_commands.v
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@@ -13,7 +13,7 @@ module tb_ultrason_commands;
wire tx_ready;
reg [7:0] data_in = 8'h00;
wire [7:0] data_out;
wire rx_received;
wire data_available;
reg rd_en = 0; // Lecture FIFO
@@ -42,13 +42,13 @@ module tb_ultrason_commands;
.BAUD_RATE(BAUD_RATE)
) uart_rx_fifo_inst (
.clk(clk),
.rx_pin(rx), // on observe la sortie du DUT
.rx_pin(tx),
.rd_en(rd_en),
.rd_data(data_out),
.data_available(rx_received)
.data_available(data_available)
);
// === TX pour injecter une commande UART vers le DUT ===
// === TX pour injecter une commande UART ===
uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
@@ -57,7 +57,7 @@ module tb_ultrason_commands;
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.data(data_in),
.tx(tx), // va dans le DUT
.tx(rx),
.rst_p(1'b0)
);
@@ -70,6 +70,7 @@ module tb_ultrason_commands;
// Attendre que le TX soit prêt
wait(tx_ready);
$display(">> TX ready");
#100;
// Envoyer la commande "ONE" (1)
@@ -77,19 +78,25 @@ module tb_ultrason_commands;
tx_enable <= 1;
#20;
tx_enable <= 0;
$display(">> Command sent: %d", data_in);
// Lire 2 octets de réponse : LSB et MSB de la distance
repeat (2) begin
wait(rx_received);
wait(data_available);
//D
#10; // Laisse le temps de valider le drapeau
rd_en <= 1; // Lecture de la FIFO
#20;
#30;
rd_en <= 0;
#200;
$display(">> Distance octet: %d", data_out);
end
$display("==== End UART Ultrasonic Test ====");
#1000;
#10000;
$stop;
end