verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

Leds

Browse Source
This commit is contained in:
Louis TANCHOU
2025-05-26 11:18:25 +02:00
parent a02d6e7d22
commit cac1a38dad
4 changed files with 54 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v
View File

@@ -2,7 +2,8 @@
module dht11_uart_top (
input clk,
inout io_dht11_sig,
output tx
output tx,
output reg [5:0] leds
);
localparam CLK_FREQ = 27_000_000; // 27 MHz
@@ -58,6 +59,8 @@ always_ff @(posedge clk) begin
delay_counter <= delay_counter + 1;
strobe2s <= 0;
end
leds[5] <= o_dht11_error;
end
always_ff @(posedge clk) begin
@@ -67,6 +70,7 @@ always_ff @(posedge clk) begin
wr_en <= 1;
wr_data <= data_fifo;
state <= WAIT;
leds [4:0] = 5'b11110;
end
WAIT: begin
i_start <= 0;
@@ -75,6 +79,7 @@ always_ff @(posedge clk) begin
state <= MESURE;
i_start <= 1;
end
leds [4:0] = 5'b11100;
end
MESURE: begin
@@ -84,17 +89,20 @@ always_ff @(posedge clk) begin
wr_data <= o_temp_data;
wr_en <= 1;
end
leds [4:0] = 5'b11000;
end
SEND_FIFO1: begin
wr_data <= o_hum_data;
wr_en <= 1;
state <= SEND_FIFO2;
leds [4:0] = 5'b10000;
end
SEND_FIFO2: begin
wr_en <= 0;
state <= WAIT;
leds [4:0] = 5'b00000;
end
default: state <= WAIT;