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Fix formatting and update LED assignment in top_uart_ultrason_command module

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Gamenight77
2025-05-12 20:40:21 +02:00
parent 2cb68ce0d1
commit cca81f4db5
1 changed files with 6 additions and 5 deletions
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11
Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
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@@ -1,9 +1,9 @@
module top_uart_ultrason_command ( module top_uart_ultrason_command (
input wire clk, // 27 MHz input wire clk, // 27 MHz
output wire tx, output wire tx,
input wire rx, input wire rx,
inout wire ultrason_sig, // Capteur ultrason inout wire ultrason_sig, // Capteur ultrason
output reg [5:0] leds output reg [5:0] leds
); );
// === UART RX WIRE === // === UART RX WIRE ===
@@ -66,7 +66,8 @@ module top_uart_ultrason_command (
always @(posedge clk) begin always @(posedge clk) begin
leds [4] <= tx; leds [4] <= data_available;
case (rx_state) case (rx_state)
IDLE: begin IDLE: begin
leds [5] <= 0; leds [5] <= 0;