Fix formatting and update LED assignment in top_uart_ultrason_command module

2025-05-12 20:40:21 +02:00
parent 2cb68ce0d1
commit cca81f4db5
1 changed files with 6 additions and 5 deletions
--- a/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
@@ -66,7 +66,8 @@ module top_uart_ultrason_command (

    always @(posedge clk) begin
        
-        leds [4] <= tx;
+        leds [4] <= data_available;
+
        case (rx_state)
            IDLE: begin
                leds [5] <= 0;