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Gamenight77
2025-05-09 09:20:56 +02:00
parent a162a2a1bb
commit cd14d82add
1 changed files with 2 additions and 1 deletions
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Semaine_4/UART/src/verilog/top_uart_loopback1.v
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@@ -118,6 +118,7 @@ localparam DATA_BYTE = 8'h31; // ASCII '1'
begin begin
// Default assignments // Default assignments
tx_enable <= 1'b0; tx_enable <= 1'b0;
leds[5:0] <= rx_data[5:0];
if (tx_ready && delay_counter == 0) begin if (tx_ready && delay_counter == 0) begin
// Start new transmission // Start new transmission
@@ -125,7 +126,7 @@ localparam DATA_BYTE = 8'h31; // ASCII '1'
data_const <= DATA_BYTE; data_const <= DATA_BYTE;
tx_data <= rx_data; tx_data <= rx_data;
leds[5:0] <= rx_data[5:0]; // Display received data on LEDs // Display received data on LEDs
delay_counter <= DELAY_CYCLES; delay_counter <= DELAY_CYCLES;
end end