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Adjust timer threshold for signal detection in DHT11 interface

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Gamenight77
2025-05-27 13:38:33 +02:00
parent 425cc8d00c
commit d69a0a4753
1 changed files with 2 additions and 2 deletions
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Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
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@@ -107,7 +107,7 @@ module dht11_interface #(
timer <= timer + 1; timer <= timer + 1;
if (sig_in == 0 && timer > 1) begin if (sig_in == 0 && timer > 2) begin
state <= RESPONSE_LOW; state <= RESPONSE_LOW;
timer <= 0; timer <= 0;
@@ -119,7 +119,7 @@ module dht11_interface #(
o_state <= state; o_state <= state;
timer <= timer + 1; timer <= timer + 1;
if (sig_in == 1) begin if (sig_in == 1 && timer > 2) begin
timer <= 0; timer <= 0;
state <= RESPONSE_HIGH; state <= RESPONSE_HIGH;