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Loopback fifo fonctionne mais avec 3 valeur de décalage

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This commit is contained in:
Gamenight77
2025-05-09 11:39:40 +02:00
parent 134df27937
commit e086ba8ef0
25 changed files with 1578 additions and 92 deletions
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18
Semaine_4/UART_FIFO/IP/verilog/fifo.v
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@@ -1,25 +1,24 @@
module fifo #(
parameter DEPTH = 16,
parameter SIZE = 16,
parameter WIDTH = 8
)(
input wire clk,
input wire wr_en,
input wire[WIDTH-1:0] wr_data,
input wire rd_en,
output wire[WIDTH-1:0] rd_data,
output reg[WIDTH-1:0] rd_data,
output wire full,
output wire empty
);
reg [WIDTH-1:0] fifo[0:DEPTH-1];
reg [WIDTH-1:0] fifo[0:SIZE-1];
reg [3:0] wr_ptr;
reg [3:0] rd_ptr;
reg [3:0] count;
assign full = (count == DEPTH);
assign full = (count == SIZE);
assign empty = (count == 0);
assign rd_data = fifo[rd_ptr];
initial begin
wr_ptr = 0;
@@ -27,15 +26,16 @@
count = 0;
end
always @(posedge clk) begin
always @(posedge clk) begin // IN
if (wr_en && !full) begin
fifo[wr_ptr] <= wr_data;
wr_ptr <= (wr_ptr + 1) % DEPTH;
wr_ptr <= (wr_ptr + 1) % SIZE;
count <= count + 1;
end
if (rd_en && !empty) begin
rd_ptr <= (rd_ptr + 1) % DEPTH;
if (rd_en && !empty) begin // OUT
rd_ptr <= (rd_ptr + 1) % SIZE;
rd_data <= fifo[rd_ptr];
count <= count - 1;
end
end

796
Semaine_4/UART_FIFO/IP/verilog/rxuartlite.v Normal file
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File diff suppressed because it is too large Load Diff

2
Semaine_4/UART_FIFO/scripts/build.bat
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@@ -19,7 +19,7 @@ if not exist runs (
)
echo === Étape 1 : Synthèse avec Yosys ===
yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx_fifo.v src/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/uart_rx.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx_fifo.v src/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/rxuartlite.v IP/verilog/uart_rx.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
if errorlevel 1 goto error
echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===

2
Semaine_4/UART_FIFO/scripts/gtkwave.bat
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@@ -1,3 +1,3 @@
@echo off
echo === Lancement de GTKWave ===
gtkwave runs/uart_rx_fifo.vcd
gtkwave runs/uart_fifo.vcd

2
Semaine_4/UART_FIFO/scripts/simulate.bat
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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=tb_uart_rx_fifo
set TOP=tb_uart_fifo
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog

62
Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v
View File

@@ -1,25 +1,21 @@
module top_uart_loopback_fifo (
input wire clk, // 27 MHz
input wire rx,
input wire clk, // 27 MHz
input wire rx,
output wire tx,
output reg [5:0] leds
output reg [5:0] leds
);
// === UART TX ===
reg [7:0] wr_data;
reg wr_en;
wire tx_fifo_full;
// UART TX
reg [7:0] wr_data = 0;
reg wr_en = 0;
wire tx_fifo_full;
// UART RX
wire [7:0] rd_data;
reg rd_en;
wire data_available;
reg rd_en = 0;
wire data_available;
initial begin
leds = 6'b111111; // Initialiser les LEDs à 0
end
// === UART RX ===
// RX FIFO Instance
uart_rx_fifo uart_rx_inst (
.clk(clk),
.rx_pin(rx),
@@ -28,7 +24,7 @@ module top_uart_loopback_fifo (
.data_available(data_available)
);
// === UART TX ===
// TX FIFO Instance
uart_tx_fifo uart_tx_inst (
.clk(clk),
.wr_en(wr_en),
@@ -37,45 +33,35 @@ module top_uart_loopback_fifo (
.tx_pin(tx)
);
// === FSM pour déclencher la transmission ===
localparam IDLE = 0, PREP_READ = 1, READ = 2, WRITE = 3;
// FSM
localparam IDLE = 2'b00, READ = 2'b01, WRITE = 2'b10;
reg [1:0] state = IDLE;
always @(posedge clk) begin
// Par défaut
wr_en <= 0;
rd_en <= 0;
// Debug visuel
leds[5] <= rx;
leds[4] <= tx;
leds[3] <= data_available;
leds[2] <= ~fifo_full;
leds <= rd_data[5:0];
case (state)
IDLE: begin
if (data_available && !fifo_full) begin
rd_en <= 1; // Mettre rd_en à 1 maintenant
state <= PREP_READ;
rd_en <= 1'b0;
wr_en <= 1'b0;
if (data_available && !tx_fifo_full) begin
rd_en <= 1'b1;
state <= READ;
end
end
PREP_READ: begin
rd_en <= 1;
state <= READ;
end
READ: begin
rd_en <= 0;
rd_en <= 1'b0;
wr_data <= rd_data;
wr_en <= 1'b1;
state <= WRITE;
end
WRITE: begin
wr_en <= 1;
wr_en <= 1'b0;
state <= IDLE;
end
endcase
end
endmodule
endmodule

22
Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v
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@@ -1,7 +1,7 @@
module uart_rx_fifo #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200,
parameter FIFO_DEPTH = 8
parameter FIFO_SIZE = 8
)(
input clk,
input rd_en,
@@ -21,22 +21,18 @@ module uart_rx_fifo #(
wire [7:0] fifo_rd_data;
// UART Receiver instance
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) uart_rx_inst (
.clk(clk),
.rst_p(1'b0),
.rx_enable(1'b1),
.rx_pin(rx_pin),
.rx_data(rx_data),
.rx_received(rx_received)
);
rxuartlite uart_rx_inst (
.i_clk(clk),
.i_reset(1'b0),
.i_uart_rx(rx_pin),
.o_wr(rx_received),
.o_data(rx_data)
);
// FIFO instance
fifo #(
.WIDTH(8),
.DEPTH(FIFO_DEPTH)
.SIZE(FIFO_SIZE)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),

4
Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v
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@@ -1,7 +1,7 @@
module uart_tx_fifo #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200,
parameter FIFO_DEPTH = 8
parameter FIFO_SIZE = 8
)(
input clk,
input wr_en,
@@ -32,7 +32,7 @@ module uart_tx_fifo #(
// FIFO instantiation
fifo #(
.WIDTH(8),
.DEPTH(FIFO_DEPTH)
.SIZE(FIFO_SIZE)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),

54
Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v
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@@ -1,49 +1,52 @@
`timescale 1ns/1ps
module tb_uart;
module tb_uart_fifo;
reg clk = 0;
reg tx_enable = 0;
reg tx_ready;
wire rx_received;
reg [7:0] data_in = 8'h00;
reg [7:0] data_out;
reg rx_received;
wire rx_enable = 1'b1;
wire pin;
wire rx;
wire tx;
always #18.5 clk = ~clk;
localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200;
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) rx_instance (
.clk(clk),
.rx_pin(pin),
.rx_data(data_out),
.rx_received(rx_received),
.rx_enable(rx_enable)
);
uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
)tx_instance (
// UART TX Instance
uart_tx emetteur_test (
.clk(clk),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.data(data_in),
.tx(pin),
.rst_p(1'b0)
.tx_ready(tx_ready),
.tx(rx)
);
// UART RX Instance
rxuartlite recepteur_test (
.i_clk(clk),
.i_reset(1'b0),
.i_uart_rx(tx),
.o_wr(rx_received),
.o_data(data_out)
);
top_uart_loopback_fifo uart (
.clk(clk),
.rx(rx),
.tx(tx)
);
initial begin
$dumpfile("runs/uart.vcd");
$dumpvars(0, tb_uart);
$dumpfile("runs/uart_fifo.vcd");
$dumpvars(0, tb_uart_fifo);
$display("======== Start UART LOOPBACK test =========");
@@ -57,7 +60,6 @@ module tb_uart;
// Attendre
wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
#1000;