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Loopback fifo fonctionne mais avec 3 valeur de décalage

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Gamenight77
2025-05-09 11:39:40 +02:00
parent 134df27937
commit e086ba8ef0
25 changed files with 1578 additions and 92 deletions
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18
Semaine_4/UART_FIFO/IP/verilog/fifo.v
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@@ -1,25 +1,24 @@
module fifo #(
parameter DEPTH = 16,
parameter SIZE = 16,
parameter WIDTH = 8
)(
input wire clk,
input wire wr_en,
input wire[WIDTH-1:0] wr_data,
input wire rd_en,
output wire[WIDTH-1:0] rd_data,
output reg[WIDTH-1:0] rd_data,
output wire full,
output wire empty
);
reg [WIDTH-1:0] fifo[0:DEPTH-1];
reg [WIDTH-1:0] fifo[0:SIZE-1];
reg [3:0] wr_ptr;
reg [3:0] rd_ptr;
reg [3:0] count;
assign full = (count == DEPTH);
assign full = (count == SIZE);
assign empty = (count == 0);
assign rd_data = fifo[rd_ptr];
initial begin
wr_ptr = 0;
@@ -27,15 +26,16 @@
count = 0;
end
always @(posedge clk) begin
always @(posedge clk) begin // IN
if (wr_en && !full) begin
fifo[wr_ptr] <= wr_data;
wr_ptr <= (wr_ptr + 1) % DEPTH;
wr_ptr <= (wr_ptr + 1) % SIZE;
count <= count + 1;
end
if (rd_en && !empty) begin
rd_ptr <= (rd_ptr + 1) % DEPTH;
if (rd_en && !empty) begin // OUT
rd_ptr <= (rd_ptr + 1) % SIZE;
rd_data <= fifo[rd_ptr];
count <= count - 1;
end
end