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Loopback fifo fonctionne mais avec 3 valeur de décalage

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This commit is contained in:
Gamenight77
2025-05-09 11:39:40 +02:00
parent 134df27937
commit e086ba8ef0
25 changed files with 1578 additions and 92 deletions
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Semaine_4/UART_FIFO/scripts/simulate.bat
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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=tb_uart_rx_fifo
set TOP=tb_uart_fifo
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog