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Loopback fifo fonctionne mais avec 3 valeur de décalage

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This commit is contained in:
Gamenight77
2025-05-09 11:39:40 +02:00
parent 134df27937
commit e086ba8ef0
25 changed files with 1578 additions and 92 deletions
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62
Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v
View File

@@ -1,25 +1,21 @@
module top_uart_loopback_fifo (
input wire clk, // 27 MHz
input wire rx,
input wire clk, // 27 MHz
input wire rx,
output wire tx,
output reg [5:0] leds
output reg [5:0] leds
);
// === UART TX ===
reg [7:0] wr_data;
reg wr_en;
wire tx_fifo_full;
// UART TX
reg [7:0] wr_data = 0;
reg wr_en = 0;
wire tx_fifo_full;
// UART RX
wire [7:0] rd_data;
reg rd_en;
wire data_available;
reg rd_en = 0;
wire data_available;
initial begin
leds = 6'b111111; // Initialiser les LEDs à 0
end
// === UART RX ===
// RX FIFO Instance
uart_rx_fifo uart_rx_inst (
.clk(clk),
.rx_pin(rx),
@@ -28,7 +24,7 @@ module top_uart_loopback_fifo (
.data_available(data_available)
);
// === UART TX ===
// TX FIFO Instance
uart_tx_fifo uart_tx_inst (
.clk(clk),
.wr_en(wr_en),
@@ -37,45 +33,35 @@ module top_uart_loopback_fifo (
.tx_pin(tx)
);
// === FSM pour déclencher la transmission ===
localparam IDLE = 0, PREP_READ = 1, READ = 2, WRITE = 3;
// FSM
localparam IDLE = 2'b00, READ = 2'b01, WRITE = 2'b10;
reg [1:0] state = IDLE;
always @(posedge clk) begin
// Par défaut
wr_en <= 0;
rd_en <= 0;
// Debug visuel
leds[5] <= rx;
leds[4] <= tx;
leds[3] <= data_available;
leds[2] <= ~fifo_full;
leds <= rd_data[5:0];
case (state)
IDLE: begin
if (data_available && !fifo_full) begin
rd_en <= 1; // Mettre rd_en à 1 maintenant
state <= PREP_READ;
rd_en <= 1'b0;
wr_en <= 1'b0;
if (data_available && !tx_fifo_full) begin
rd_en <= 1'b1;
state <= READ;
end
end
PREP_READ: begin
rd_en <= 1;
state <= READ;
end
READ: begin
rd_en <= 0;
rd_en <= 1'b0;
wr_data <= rd_data;
wr_en <= 1'b1;
state <= WRITE;
end
WRITE: begin
wr_en <= 1;
wr_en <= 1'b0;
state <= IDLE;
end
endcase
end
endmodule
endmodule

22
Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v
View File

@@ -1,7 +1,7 @@
module uart_rx_fifo #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200,
parameter FIFO_DEPTH = 8
parameter FIFO_SIZE = 8
)(
input clk,
input rd_en,
@@ -21,22 +21,18 @@ module uart_rx_fifo #(
wire [7:0] fifo_rd_data;
// UART Receiver instance
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) uart_rx_inst (
.clk(clk),
.rst_p(1'b0),
.rx_enable(1'b1),
.rx_pin(rx_pin),
.rx_data(rx_data),
.rx_received(rx_received)
);
rxuartlite uart_rx_inst (
.i_clk(clk),
.i_reset(1'b0),
.i_uart_rx(rx_pin),
.o_wr(rx_received),
.o_data(rx_data)
);
// FIFO instance
fifo #(
.WIDTH(8),
.DEPTH(FIFO_DEPTH)
.SIZE(FIFO_SIZE)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),

4
Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v
View File

@@ -1,7 +1,7 @@
module uart_tx_fifo #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200,
parameter FIFO_DEPTH = 8
parameter FIFO_SIZE = 8
)(
input clk,
input wr_en,
@@ -32,7 +32,7 @@ module uart_tx_fifo #(
// FIFO instantiation
fifo #(
.WIDTH(8),
.DEPTH(FIFO_DEPTH)
.SIZE(FIFO_SIZE)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),