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Loopback fifo fonctionne mais avec 3 valeur de décalage

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Gamenight77
2025-05-09 11:39:40 +02:00
parent 134df27937
commit e086ba8ef0
25 changed files with 1578 additions and 92 deletions
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54
Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v
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@@ -1,49 +1,52 @@
`timescale 1ns/1ps
module tb_uart;
module tb_uart_fifo;
reg clk = 0;
reg tx_enable = 0;
reg tx_ready;
wire rx_received;
reg [7:0] data_in = 8'h00;
reg [7:0] data_out;
reg rx_received;
wire rx_enable = 1'b1;
wire pin;
wire rx;
wire tx;
always #18.5 clk = ~clk;
localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200;
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) rx_instance (
.clk(clk),
.rx_pin(pin),
.rx_data(data_out),
.rx_received(rx_received),
.rx_enable(rx_enable)
);
uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
)tx_instance (
// UART TX Instance
uart_tx emetteur_test (
.clk(clk),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.data(data_in),
.tx(pin),
.rst_p(1'b0)
.tx_ready(tx_ready),
.tx(rx)
);
// UART RX Instance
rxuartlite recepteur_test (
.i_clk(clk),
.i_reset(1'b0),
.i_uart_rx(tx),
.o_wr(rx_received),
.o_data(data_out)
);
top_uart_loopback_fifo uart (
.clk(clk),
.rx(rx),
.tx(tx)
);
initial begin
$dumpfile("runs/uart.vcd");
$dumpvars(0, tb_uart);
$dumpfile("runs/uart_fifo.vcd");
$dumpvars(0, tb_uart_fifo);
$display("======== Start UART LOOPBACK test =========");
@@ -57,7 +60,6 @@ module tb_uart;
// Attendre
wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
#1000;