struct

Help/presentation_examples/blink/tests/verilog/blink_tb.v

@@ -0,0 +1,37 @@
+`timescale 1ns/1ps
+`default_nettype none
+
+module blink_tb ();
+
+reg clk = 0;
+
+initial forever #5 clk = !clk;
+
+wire led;
+
+
+blink #(.CLK_SPEED(20)) bl (.clk(clk),.led(led));
+
+
+initial begin
+`ifdef VCD_DUMP
+  $dumpfile("blink_tb.vcd");
+  $dumpvars(0,blink_tb);
+`endif
+end 
+
+
+initial begin
+`ifdef END_TIME
+    #`END_TIME $finish();
+`else
+    #1000 $finish();
+`endif
+end
+
+initial begin
+
+    #500 $finish();   
+end
+
+endmodule