struct

Help/presentation_examples/blink_vivado/src/verilog/blink.v

@@ -0,0 +1,34 @@
+`timescale 1ns/1ps
+`default_nettype none
+module blink #(
+    parameter CLK_SPEED = 27_000_000
+)
+(
+    input wire clk,
+    output reg led
+);
+
+wire strobe;
+
+localparam ONE_HALF_S = CLK_SPEED / 2;
+localparam ONE_S = CLK_SPEED ;
+localparam TWO_S = CLK_SPEED *2;
+
+
+localparam TIME = TWO_S;
+localparam TIME_WIDTH = $clog2(TIME);
+
+initial led = 0;
+
+counter  #(.WIDTH(TIME_WIDTH), .INITIAL_VALUE(TIME)) counter_inst
+(
+    .clk(clk),
+    .reset(1'b0),
+    .en(1'b1),
+    .strobe(strobe)
+);
+
+always_ff @(posedge clk)
+   if(strobe) led <= !led;
+
+endmodule